1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <console/console.h>
4 #include <baseboard/variants.h>
5 #include <device/device.h>
6 #include <drivers/tpm/cr50.h>
7 #include <ec/ec.h>
8 #include <fw_config.h>
9 #include <gpio.h>
10 #include <intelblocks/gpio.h>
11 #include <security/tpm/tss.h>
12 #include <intelblocks/tcss.h>
13 #include <soc/pci_devs.h>
14 #include <soc/ramstage.h>
15 #include <stdio.h>
16 #include <variant/gpio.h>
17 #include <vb2_api.h>
18
19 #include "drivers/intel/pmc_mux/conn/chip.h"
20
21 WEAK_DEV_PTR(conn1);
22
typec_orientation_fixup(void)23 static void typec_orientation_fixup(void)
24 {
25 const struct device *conn = DEV_PTR(conn1);
26
27 if (!is_dev_enabled(conn))
28 return;
29
30 if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2))
31 || fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE))
32 || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))
33 || fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) {
34 struct drivers_intel_pmc_mux_conn_config *config = conn->chip_info;
35
36 if (config) {
37 printk(BIOS_INFO,
38 "Configure Right Type-C port orientation for retimer\n");
39 config->sbu_orientation = TYPEC_ORIENTATION_NORMAL;
40 }
41 }
42 }
43
mainboard_init(struct device * dev)44 static void mainboard_init(struct device *dev)
45 {
46 mainboard_ec_init();
47 typec_orientation_fixup();
48 variant_devtree_update();
49 }
50
variant_devtree_update(void)51 void __weak variant_devtree_update(void)
52 {
53 }
54
variant_ramstage_init(void)55 void __weak variant_ramstage_init(void)
56 {
57 /* Default weak implementation */
58 }
59
add_fw_config_oem_string(const struct fw_config * config,void * arg)60 static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
61 {
62 struct smbios_type11 *t;
63 char buffer[64];
64
65 t = (struct smbios_type11 *)arg;
66
67 snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name);
68 t->count = smbios_add_string(t->eos, buffer);
69 }
70
mainboard_smbios_strings(struct device * dev,struct smbios_type11 * t)71 static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
72 {
73 fw_config_for_each_found(add_fw_config_oem_string, t);
74 }
75
mainboard_enable(struct device * dev)76 static void mainboard_enable(struct device *dev)
77 {
78 dev->ops->init = mainboard_init;
79 dev->ops->get_smbios_strings = mainboard_smbios_strings;
80
81 variant_ramstage_init();
82 }
83
mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config * cfg)84 void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
85 {
86 tpm_result_t rc;
87 if (!CONFIG(TPM_GOOGLE_CR50) || !CONFIG(SPI_TPM)) {
88 /*
89 * Negotiation of long interrupt pulses is only supported via SPI. I2C is only
90 * used on reworked prototypes on which the TPM is replaced with Dauntless under
91 * development, it will use long pulses by default, or use the interrupt line in
92 * a different way altogether.
93 */
94 return;
95 }
96
97 rc = tlcl_lib_init();
98 if (rc != TPM_SUCCESS) {
99 printk(BIOS_ERR, "tlcl_lib_init() failed: %#x\n", rc);
100 return;
101 }
102
103 if (cr50_is_long_interrupt_pulse_enabled()) {
104 printk(BIOS_INFO, "Enabling S0i3.4\n");
105 } else {
106 /*
107 * Disable S0i3.4, preventing the GPIO block from switching to
108 * slow clock.
109 */
110 printk(BIOS_INFO, "Not enabling S0i3.4\n");
111 cfg->LpmStateDisableMask |= LPM_S0i3_4;
112 cfg->gpio_override_pm = 1;
113 memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm));
114 }
115 }
116
mainboard_chip_init(void * chip_info)117 static void mainboard_chip_init(void *chip_info)
118 {
119 const struct pad_config *base_pads;
120 const struct pad_config *override_pads;
121 size_t base_num, override_num;
122
123 base_pads = baseboard_gpio_table(&base_num);
124 override_pads = variant_override_gpio_table(&override_num);
125
126 gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
127
128 /*
129 * Check SATAXPCIE1 (GPP_A12) RX status to determine if SSD is NVMe or SATA and set
130 * the IOSSTATE RX field to drive 0 or 1 back to the internal controller to ensure
131 * the attached device is not mis-detected on resume from S0ix.
132 */
133 if (gpio_get(GPP_A12)) {
134 const struct pad_config gpio_pedet_nvme[] = {
135 PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx1),
136 };
137 gpio_configure_pads(gpio_pedet_nvme, ARRAY_SIZE(gpio_pedet_nvme));
138 printk(BIOS_INFO, "SATAXPCIE1 indicates PCIe NVMe is present\n");
139 } else {
140 const struct pad_config gpio_pedet_sata[] = {
141 PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx0),
142 };
143 gpio_configure_pads(gpio_pedet_sata, ARRAY_SIZE(gpio_pedet_sata));
144 printk(BIOS_INFO, "SATAXPCIE1 indicates SATA SSD is present\n");
145 }
146 }
147
148 struct chip_operations mainboard_ops = {
149 .init = mainboard_chip_init,
150 .enable_dev = mainboard_enable,
151 };
152