1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <amdblocks/acpi.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/mmio.h>
7 #include <acpi/acpi.h>
8 #include <acpi/acpigen.h>
9 #include <amdblocks/amd_pci_util.h>
10 #include <amdblocks/smi.h>
11 #include <baseboard/variants.h>
12 #include <boardid.h>
13 #include <gpio.h>
14 #include <smbios.h>
15 #include <soc/cpu.h>
16 #include <soc/pci_devs.h>
17 #include <soc/platform_descriptors.h>
18 #include <soc/southbridge.h>
19 #include <soc/smi.h>
20 #include <soc/soc_util.h>
21 #include <amdblocks/acpimmio.h>
22 #include <variant/ec.h>
23 #include <variant/thermal.h>
24 #include <commonlib/helpers.h>
25
26 #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN"
27 #define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS"
28 #define METHOD_MAINBOARD_INI "\\_SB.MINI"
29 #define METHOD_MAINBOARD_WAK "\\_SB.MWAK"
30 #define METHOD_MAINBOARD_PTS "\\_SB.MPTS"
31
32 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
33 accessed via I/O ports 0xc00/0xc01. */
34
35 /*
36 * This controls the device -> IRQ routing.
37 *
38 * Hardcoded IRQs:
39 * 0: timer < soc/amd/common/acpi/lpc.asl
40 * 1: i8042 <- ec/google/chromeec/acpi/superio.asl
41 * 2: cascade
42 * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
43 * 9: acpi <- soc/amd/common/acpi/lpc.asl
44 * 12: i8042 <- ec/google/chromeec/acpi/superio.asl
45 */
46 static const struct fch_irq_routing fch_irq_map[] = {
47 { PIRQ_A, 6, PIRQ_NC },
48 { PIRQ_B, 13, PIRQ_NC },
49 { PIRQ_C, 14, PIRQ_NC },
50 { PIRQ_D, 15, PIRQ_NC },
51 { PIRQ_E, 15, PIRQ_NC },
52 { PIRQ_F, 14, PIRQ_NC },
53 { PIRQ_G, 13, PIRQ_NC },
54 { PIRQ_H, 6, PIRQ_NC },
55
56 { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
57 { PIRQ_EMMC, 5, 5 },
58 { PIRQ_GPIO, 7, 7 },
59 { PIRQ_I2C2, 10, 10 },
60 { PIRQ_I2C3, 11, 11 },
61 { PIRQ_UART0, 4, 4 },
62 { PIRQ_UART1, 3, 3 },
63
64 /* The MISC registers are not interrupt numbers */
65 { PIRQ_MISC, 0xfa, 0x00 },
66 { PIRQ_MISC0, 0x91, 0x00 },
67 { PIRQ_MISC1, 0x00, 0x00 },
68 { PIRQ_MISC2, 0x00, 0x00 },
69 };
70
mb_get_fch_irq_mapping(size_t * length)71 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
72 {
73 *length = ARRAY_SIZE(fch_irq_map);
74 return fch_irq_map;
75 }
76
mainboard_configure_gpios(void)77 static void mainboard_configure_gpios(void)
78 {
79 size_t base_num_gpios, override_num_gpios;
80 const struct soc_amd_gpio *base_gpios, *override_gpios;
81
82 base_gpios = baseboard_gpio_table(&base_num_gpios);
83 override_gpios = variant_override_gpio_table(&override_num_gpios);
84
85 gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios,
86 override_num_gpios);
87 }
88
mainboard_devtree_update(void)89 static void mainboard_devtree_update(void)
90 {
91 variant_audio_update();
92 variant_bluetooth_update();
93 variant_touchscreen_update();
94 variant_devtree_update();
95 }
96
mainboard_init(void * chip_info)97 static void mainboard_init(void *chip_info)
98 {
99 int boardid;
100
101 mainboard_ec_init();
102 boardid = board_id();
103 printk(BIOS_INFO, "Board ID: %d\n", boardid);
104
105 mainboard_configure_gpios();
106
107 /* Update DUT configuration */
108 mainboard_devtree_update();
109 }
110
mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor ** dxio_descs,size_t * dxio_num,const fsp_ddi_descriptor ** ddi_descs,size_t * ddi_num)111 void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
112 size_t *dxio_num,
113 const fsp_ddi_descriptor **ddi_descs,
114 size_t *ddi_num)
115 {
116 variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num);
117 }
118
mainboard_write_blken(void)119 static void mainboard_write_blken(void)
120 {
121 acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0);
122 acpigen_soc_clear_tx_gpio(GPIO_85);
123 acpigen_pop_len();
124 }
125
mainboard_write_blkdis(void)126 static void mainboard_write_blkdis(void)
127 {
128 acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0);
129 acpigen_soc_set_tx_gpio(GPIO_85);
130 acpigen_pop_len();
131 }
132
mainboard_write_mini(void)133 static void mainboard_write_mini(void)
134 {
135 acpigen_write_method(METHOD_MAINBOARD_INI, 0);
136 acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
137 acpigen_pop_len();
138 }
139
mainboard_write_mwak(void)140 static void mainboard_write_mwak(void)
141 {
142 acpigen_write_method(METHOD_MAINBOARD_WAK, 0);
143 acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
144 acpigen_pop_len();
145 }
146
mainboard_write_mpts(void)147 static void mainboard_write_mpts(void)
148 {
149 acpigen_write_method(METHOD_MAINBOARD_PTS, 0);
150 acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE);
151 acpigen_pop_len();
152 }
153
mainboard_fill_ssdt(const struct device * dev)154 static void mainboard_fill_ssdt(const struct device *dev)
155 {
156 mainboard_write_blken();
157 mainboard_write_blkdis();
158 mainboard_write_mini();
159 mainboard_write_mpts();
160 mainboard_write_mwak();
161 }
162
163 /*************************************************
164 * Dedicated mainboard function
165 *************************************************/
mainboard_enable(struct device * dev)166 static void mainboard_enable(struct device *dev)
167 {
168 dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
169 }
170
mainboard_final(void * chip_info)171 static void mainboard_final(void *chip_info)
172 {
173 finalize_gpios(acpi_get_sleep_type());
174 }
175
176 struct chip_operations mainboard_ops = {
177 .init = mainboard_init,
178 .enable_dev = mainboard_enable,
179 .final = mainboard_final,
180 };
181
variant_devtree_update(void)182 void __weak variant_devtree_update(void)
183 {
184 }
185
variant_override_gpio_table(size_t * size)186 __weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
187 {
188 /* Default weak implementation - No overrides. */
189 *size = 0;
190 return NULL;
191 }
192