1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootblock_common.h>
4 #include <device/pnp_ops.h>
5 #include <device/pnp_def.h>
6 #include <northbridge/intel/i945/i945.h>
7 #include <southbridge/intel/i82801gx/i82801gx.h>
8 #include <superio/winbond/common/winbond.h>
9 #include <superio/winbond/w83627ehg/w83627ehg.h>
10
11 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
12
13 /* This box has one superio
14 * Also set up the GPIOs from the beginning. This is the "no schematic
15 * but safe anyways" method.
16 */
bootblock_mainboard_early_init(void)17 void bootblock_mainboard_early_init(void)
18 {
19 pnp_devfn_t dev;
20
21 dev = SUPERIO_DEV;
22 pnp_enter_conf_state(dev);
23
24 pnp_write_config(dev, 0x24, 0xc4); // PNPCVS
25
26 pnp_write_config(dev, 0x29, 0x01); // GPIO settings
27 pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
28 pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
29 pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
30 pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
31
32 dev = PNP_DEV(0x4e, W83627EHG_SP1);
33 pnp_set_logical_device(dev);
34 pnp_set_enable(dev, 0);
35 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
36 pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
37 pnp_set_enable(dev, 1);
38
39 dev = PNP_DEV(0x4e, W83627EHG_SP2);
40 pnp_set_logical_device(dev);
41 pnp_set_enable(dev, 0);
42 pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
43 pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
44 // pnp_write_config(dev, PNP_IDX_MSC1, 4); // IRMODE0
45 pnp_set_enable(dev, 1);
46
47 dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
48 pnp_set_logical_device(dev);
49 pnp_set_enable(dev, 0);
50 pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
51 pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
52 //pnp_write_config(dev, PNP_IDX_MSC0, 0x82);
53 pnp_set_enable(dev, 1);
54
55 dev = PNP_DEV(0x4e, W83627EHG_GPIO2);
56 pnp_set_logical_device(dev);
57 pnp_set_enable(dev, 1); // Just enable it
58
59 dev = PNP_DEV(0x4e, W83627EHG_GPIO3);
60 pnp_set_logical_device(dev);
61 pnp_set_enable(dev, 0);
62 pnp_write_config(dev, PNP_IDX_MSC0, 0xfb); // GPIO bit 2 is output
63 pnp_write_config(dev, PNP_IDX_MSC1, 0x00); // GPIO bit 2 is 0
64 // Enable GPIO3+4. pnp_set_enable is not sufficient
65 pnp_write_config(dev, PNP_IDX_EN, 0x03);
66
67 dev = PNP_DEV(0x4e, W83627EHG_FDC);
68 pnp_set_logical_device(dev);
69 pnp_set_enable(dev, 0);
70
71 dev = PNP_DEV(0x4e, W83627EHG_PP);
72 pnp_set_logical_device(dev);
73 pnp_set_enable(dev, 0);
74
75 /* Enable HWM */
76 dev = PNP_DEV(0x4e, W83627EHG_HWM);
77 pnp_set_logical_device(dev);
78 pnp_set_enable(dev, 0);
79 pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
80 pnp_set_enable(dev, 1);
81
82 pnp_exit_conf_state(dev);
83 }
84
mainboard_late_rcba_config(void)85 void mainboard_late_rcba_config(void)
86 {
87 /* Device 1f interrupt pin register */
88 RCBA32(D31IP) = 0x00042210;
89 /* Device 1d interrupt pin register */
90 RCBA32(D28IP) = 0x00214321;
91
92 /* dev irq route register */
93 RCBA16(D31IR) = 0x0132;
94 RCBA16(D30IR) = 0x0146;
95 RCBA16(D29IR) = 0x0237;
96 RCBA16(D28IR) = 0x3201;
97 RCBA16(D27IR) = 0x0146;
98 }
99