1FLASH 32M { 2 SI_ALL 6M { 3 SI_DESC 4K 4 SI_EC 512K 5 SI_ME { 6 CSE_LAYOUT 8K 7 CSE_RO 1588K 8 CSE_DATA 512K 9 # 64-KiB aligned to optimize RW erases during CSE update. 10 CSE_RW 3520K 11 } 12 } 13 SI_BIOS 26M { 14 RW_SECTION_A 8M { 15 VBLOCK_A 64K 16 FW_MAIN_A(CBFS) 17 RW_FWID_A 64 18 } 19 RW_LEGACY(CBFS) 1M 20 RW_MISC 1M { 21 UNIFIED_MRC_CACHE(PRESERVE) 192K { 22 RECOVERY_MRC_CACHE 64K 23 RW_MRC_CACHE 128K 24 } 25 RW_ELOG(PRESERVE) 16K 26 RW_SHARED 16K { 27 SHARED_DATA 8K 28 VBLOCK_DEV 8K 29 } 30 RW_VPD(PRESERVE) 8K 31 RW_NVRAM(PRESERVE) 24K 32 } 33 # This section starts at the 16M boundary in SPI flash. 34 # ADL does not support a region crossing this boundary, 35 # because the SPI flash is memory-mapped into two non- 36 # contiguous windows. 37 RW_SECTION_B 8M { 38 VBLOCK_B 64K 39 FW_MAIN_B(CBFS) 40 RW_FWID_B 64 41 } 42 # Make WP_RO region align with SPI vendor 43 # memory protected range specification. 44 WP_RO 8M { 45 RO_VPD(PRESERVE) 16K 46 RO_SECTION { 47 FMAP 2K 48 RO_FRID 64 49 GBB@4K 448K 50 COREBOOT(CBFS) 51 } 52 } 53 } 54} 55