1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <types.h>
6 #include <vendorcode/google/chromeos/chromeos.h>
7
8 /* Pad configuration in ramstage */
9 static const struct pad_config gpio_table[] = {
10 /* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
11 eSPI is enabled */
12
13 /* SSD1_PWREN CPU SSD1 */
14 PAD_CFG_GPO(GPP_D14, 1, PLTRST),
15 /* SSD1_RESET CPU SSD1 */
16 PAD_CFG_GPO(GPP_F20, 1, PLTRST),
17 /* BT_RF_KILL_N */
18 PAD_CFG_GPO(GPP_A13, 1, PLTRST),
19 /* WLAN RST# */
20 PAD_CFG_GPO(GPP_H2, 1, PLTRST),
21 /* WIFI_WAKE_N */
22 PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
23 /* x4 PCIE slot1 PWREN */
24 PAD_CFG_GPO(GPP_H17, 0, PLTRST),
25 /* x4 PCIE slot 1 RESET */
26 PAD_CFG_GPO(GPP_F10, 1, PLTRST),
27 /* Retimer Force Power */
28 PAD_CFG_GPO(GPP_E4, 0, PLTRST),
29 /* PEG Slot RST# */
30 PAD_CFG_GPO(GPP_B2, 1, PLTRST),
31 /* M.2 SSD_2 Reset */
32 PAD_CFG_GPO(GPP_H0, 1, PLTRST),
33 /* CAM_STROBE */
34 PAD_CFG_GPO(GPP_B18, 0, PLTRST),
35 /* Audio Codec INT N */
36 PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
37 /* TCH PAD Power EN */
38 PAD_CFG_GPO(GPP_F7, 1, PLTRST),
39 /* THC1 SPI2 RST# */
40 PAD_CFG_GPO(GPP_F17, 1, PLTRST),
41 /* THC1_SPI2_INTB */
42 PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
43 /* THC1_SPI2_INTB */
44 PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
45 /* EC_SLP_S0_CS_N */
46 PAD_CFG_GPO(GPP_F9, 1, PLTRST),
47 /* DISP_AUX_N_BIAS_GPIO */
48 PAD_CFG_GPO(GPP_E23, 1, PLTRST),
49 /* WWAN WAKE N*/
50 PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
51 /* WWAN_DISABLE_N */
52 PAD_CFG_GPO(GPP_D15, 1, DEEP),
53 /* WWAN_RST# */
54 PAD_CFG_GPO(GPP_F14, 1, DEEP),
55 /* WWAN_FCP_OFF_N */
56 PAD_CFG_GPO(GPP_F15, 1, DEEP),
57 /* WWAN_PWR_EN */
58 PAD_CFG_GPO(GPP_F21, 1, DEEP),
59 /* WWAN_PERST# */
60 PAD_CFG_GPO(GPP_C5, 1, DEEP),
61 /* PEG_SLOT_WAKE_N */
62 PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
63 /* CAM CONN1 CLKEN */
64 PAD_CFG_GPO(GPP_H15, 1, PLTRST),
65 /* CPU SSD2 PWREN */
66 PAD_CFG_GPO(GPP_C2, 1, PLTRST),
67 /* CPU SSD2 RST# */
68 PAD_CFG_GPO(GPP_H1, 1, PLTRST),
69 /* Sata direct Power */
70 PAD_CFG_GPO(GPP_B4, 1, PLTRST),
71 /* M.2_PCH_SSD_PWREN */
72 PAD_CFG_GPO(GPP_D16, 1, PLTRST),
73
74 /* CAM1_RST */
75 PAD_CFG_GPO(GPP_R5, 1, PLTRST),
76 /* CAM2_RST */
77 PAD_CFG_GPO(GPP_E15, 1, PLTRST),
78 /* CAM1_PWR_EN */
79 PAD_CFG_GPO(GPP_B23, 1, PLTRST),
80 /* CAM2_PWR_EN */
81 PAD_CFG_GPO(GPP_E16, 1, PLTRST),
82 /* M.2_SSD_PDET_R */
83 PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
84 /* THC0 SPI1 CLK */
85 PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
86 /* THC0 SPI1 IO 1 */
87 PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2),
88 /* THC0 SPI1 IO 2 */
89 PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
90 /* THC0 SPI IO 3 */
91 PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
92 /* THC1 SPI1 RSTB */
93 PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2),
94 /* UART_RX(1) */
95 PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
96 /* UART_RX(2) */
97 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
98 /* UART_RX(4) */
99 PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
100 /* UART_RX(5) */
101 PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1),
102 /* UART_RX(6) */
103 PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1),
104
105 /* UART_TX(1) */
106 PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
107 /* UART_TX(2) */
108 PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
109 /* UART_TX(4) */
110 PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1),
111 /* UART_TX(5) */
112 PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1),
113 /* UART_TX(6) */
114 PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1),
115
116 /* UART_RTS(1) */
117 PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
118 /* UART_RTS(2) */
119 PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
120 /* UART_RTS(4) */
121 PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
122 /* UART_RTS(5) */
123 PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1),
124 /* UART_RTS(6) */
125 PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1),
126
127 /* UART_CTS(1) */
128 PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
129 /* UART_CTS(2) */
130 PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
131 /* UART_CTS(4) */
132 PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
133 /* UART_CTS(5) */
134 PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1),
135 /* UART_CTS(6) */
136 PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1),
137
138 /* SPI_MOSI(1) */
139 PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
140 /* SPI_MOSI(2) */
141 PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
142
143 /* SPI_MIS0(1) */
144 PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
145 /* SPI_MIS0(2) */
146 PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
147
148 /* SPI_CLK(1) */
149 PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
150 /* SPI_CLK(2) */
151 PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
152
153 /* SPI_CS(0, 1) */
154 PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
155 /* SPI_CS(1, 0) */
156 PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
157 /* SPI_CS(2, 0) */
158 PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
159
160 /* I2C_SCL(0) */
161 PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
162 /* I2C_SCL(1) */
163 PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
164 /* I2C_SCL(2) */
165 PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
166 /* I2C_SCL(3) */
167 PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
168 /* I2C_SCL(5) */
169 PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
170
171 /* I2C_SDA(0) */
172 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
173 /* I2C_SDA(1) */
174 PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
175 /* I2C_SDA(2) */
176 PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
177 /* I2C_SDA(3) */
178 PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
179 /* I2C_SDA(5) */
180 PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
181
182 /* I2S0_SCLK */
183 PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
184 /* I2S0_SFRM */
185 PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
186 /* I2S0_TXD */
187 PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
188 /* I2S0_RXD */
189 PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
190
191 /* I2S_MCLK1_OUT */
192 PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
193 /* I2S_MCLK2_INOUT */
194 PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
195
196 /* SNDW1_CLK */
197 PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
198 /* SNDW1_DATA */
199 PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
200 /* SNDW2_CLK */
201 PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
202 /* SNDW2_DATA */
203 PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
204 /* SNDW3_CLK */
205 PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
206 /* SNDW3_DATA */
207 PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
208 /* SNDW4_CLK */
209 PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
210 /* SNDW4_DATA */
211 PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
212
213 /* SMB_CLK */
214 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
215 /* SMB_DATA */
216 PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
217
218 /* SATA DEVSLP */
219 PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
220 PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
221
222 /* SATA LED pin */
223 PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
224
225 /* USB2 OC0 pins */
226 PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
227 /* USB2 OC3 pins */
228 PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
229
230 /* GPIO pin for PCIE SRCCLKREQB */
231 PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
232 PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
233 PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
234 PAD_NC(GPP_D8, NONE),
235 PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
236 PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
237 PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
238
239 /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */
240 PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
241 PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
242 PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
243 PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
244 PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
245 PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
246 PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
247
248 /* HPD_1 (E14) and HPD_2 (A18) pins */
249 PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
250 PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
251
252 /* IMGCLKOUT */
253 PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
254 PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
255 PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
256 PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
257 /* H23 : CLKREQ5_WWAN_N */
258 PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
259
260 /* A21 : HDMI CRLS CTRLCLK */
261 PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
262 /* A22 : HDMI CRLS CTRLDATA */
263 PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
264 /* H1_PCH_INT_ODL */
265 PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT)
266 };
267
variant_configure_gpio_pads(void)268 void variant_configure_gpio_pads(void)
269 {
270 gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
271 }
272
273 static const struct cros_gpio cros_gpios[] = {
274 CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
275 };
276 DECLARE_CROS_GPIOS(cros_gpios);
277