1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <commonlib/helpers.h>
6 #include <vendorcode/google/chromeos/chromeos.h>
7
8 /* Pad configuration in ramstage*/
9 static const struct pad_config gpio_table[] = {
10 /* ESPI_IO0_EC_R / ESPI_IO0_HDR */
11 PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
12 /* ESPI_IO1_EC_R / ESPI_IO1_HDR */
13 PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
14 /* ESPI_IO2_EC_R / ESPI_IO2_HDR */
15 PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
16 /* ESPI_IO3_EC_R / ESPI_IO3_HDR */
17 PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
18 /* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */
19 PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
20 /* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */
21 PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
22 /* ESPI_CLK_EC_R / ESPI_CLK_HDR */
23 PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
24 /* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */
25 PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
26
27 /* EC_SLP_S0_CS_N */
28 PAD_CFG_GPO(GPP_E4, 1, PLTRST),
29
30 /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
31 PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
32 /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
33 PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
34
35 /* M.2_SSD_PDET_R */
36 PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
37 /* CLKREQ0_M2_SSD_N */
38 PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
39 /* M2_PCH_SSD_PWREN */
40 PAD_CFG_GPO(GPP_D16, 1, PLTRST),
41 /* M2_SSD_RST_N */
42 PAD_CFG_GPO(GPP_H0, 1, PLTRST),
43 /* M2_SSD_DEVSLP */
44 PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
45
46 /* I5 : NC */
47 PAD_NC(GPP_I5, NONE),
48 /* I7 : EMMC_CMD ==> EMMC_CMD */
49 PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
50 /* I8 : EMMC_DATA0 ==> EMMC_D0 */
51 PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
52 /* I9 : EMMC_DATA1 ==> EMMC_D1 */
53 PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
54 /* I10 : EMMC_DATA2 ==> EMMC_D2 */
55 PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
56 /* I11 : EMMC_DATA3 ==> EMMC_D3 */
57 PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
58 /* I12 : EMMC_DATA4 ==> EMMC_D4 */
59 PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
60 /* I13 : EMMC_DATA5 ==> EMMC_D5 */
61 PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
62 /* I14 : EMMC_DATA6 ==> EMMC_D6 */
63 PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
64 /* I15 : EMMC_DATA7 ==> EMMC_D7 */
65 PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
66 /* I16 : EMMC_RCLK ==> EMMC_RCLK */
67 PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
68 /* I17 : EMMC_CLK ==> EMMC_CLK */
69 PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
70 /* I18 : EMMC_RESET# ==> EMMC_RST_L */
71 PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
72
73 /* TYPEA_CONN23_USB2_P8_OC1_N */
74 PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
75 /* CRD1_PWREN */
76 PAD_CFG_GPO(GPP_B23, 1, PLTRST),
77 /* TCP1_DISP_AUX_P_BIAS_GPIO */
78 PAD_CFG_GPO(GPP_E20, 1, PLTRST),
79 /* TCP1_DISP_AUX_N_BIAS_GPIO */
80 PAD_CFG_GPO(GPP_E21, 0, PLTRST),
81 /* TCP0_DISP_AUX_P_BIAS_GPIO */
82 PAD_CFG_GPO(GPP_E22, 0, PLTRST),
83 /* TCP0_DISP_AUX_N_BIAS_GPIO */
84 PAD_CFG_GPO(GPP_E23, 1, PLTRST),
85
86 /* EDP1_HPD_MIPI_PNL_RST */
87 PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
88
89 /* X1_SLOT_PWREN */
90 PAD_CFG_GPO(GPP_A8, 0, PLTRST),
91 /* SML0_CLK */
92 PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
93 /* SML0_DATA */
94 PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
95 /* CLKREQ3_X1PCIE_SLOT_N */
96 PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
97 /* X1_PCIE_SLOT_WAKE_N */
98 PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT),
99 /* X1_Slot_RESET */
100 PAD_CFG_GPO(GPP_F10, 1, PLTRST),
101
102 /* WWAN_PERST_N */
103 PAD_CFG_GPO(GPP_C5, 1, PLTRST),
104 /* CLKREQ1_WWAN_N */
105 PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
106 /* GPPC_D15_M.2_WWAN_DISABLE_N */
107 PAD_CFG_GPO(GPP_D15, 1, PLTRST),
108 /* WWAN_PWREN */
109 PAD_CFG_GPO(GPP_D17, 1, PLTRST),
110 /* WWAN WAKE N */
111 PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI
112 /* SRCCLK_OEB6 */
113 PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3),
114 /* GPPC_F6_CNV_PA_BLANKING */
115 PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
116 /* WWAN_RST# */
117 PAD_CFG_GPO(GPP_F14, 1, PLTRST),
118 /* WWAN_FCP_OFF_N */
119 PAD_CFG_GPO(GPP_F15, 1, PLTRST),
120 /* CNV_MFUART2_RXD */
121 PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
122 /* CNV_MFUART2_RXD */
123 PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
124
125 /* PM_SLP_S0_N */
126 PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
127 /* PLT_RST_N */
128 PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
129 /* PM_SLP_DRAM_N */
130 PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
131 /* CPU_C10_GATE_N_R */
132 PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
133
134 /* CODEC_INT_N */
135 PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
136 /* SNDW0_CLK_HDR */
137 PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
138 /* SNDW0_DATA_HDR */
139 PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
140 /* SNDW1_CLK_DMIC_CLK_A_0 */
141 PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
142 /* SNDW1_DATA_DMIC_DATA_0 */
143 PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
144 /* SNDW2_CLK_R */
145 PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
146 /* SNDW2_DATA_R */
147 PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
148 /* SOC_DMIC0_SNDW3_CLK */
149 PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
150 /* SOC_DMIC0_SNDW3_DATA */
151 PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
152
153 /* I2C_SCL(0) */
154 PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
155 /* I2C_SDA(0) */
156 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
157
158 /* DDIB_DP_HDMI_ALS_HDP */
159 PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
160
161 /* 8 : M.2_BTWIFI_SUS_CLK */
162 PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
163 /* 9 : GPD_9_SLP_WLAN_N */
164 PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
165
166 /* SRCCLK_OEB7 */
167 PAD_CFG_GPO(GPP_A7, 0, PLTRST),
168
169 /* GPIO pin for PCIE SRCCLKREQB_2 */
170 PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
171
172 /* H2 : WLAN_RST_N */
173 PAD_CFG_GPO(GPP_H2, 1, PLTRST),
174 /* I2C_SDA(1) */
175 PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
176 /* I2C_SCL(1) */
177 PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
178
179 /* CAM_PRIVACY_LED */
180 PAD_CFG_GPO(GPP_B14, 1, PLTRST),
181
182 /* B16 : I2C5 SDA */
183 PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
184 /* B17 : I2C5 SCL */
185 PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
186
187 /* CAM_STROBE */
188 PAD_CFG_GPO(GPP_B18, 0, PLTRST),
189 /* CAM1_RST_N */
190 PAD_CFG_GPO(GPP_A21, 1, PLTRST),
191 /* CAM1_PWR_EN */
192 PAD_CFG_GPO(GPP_B23, 1, PLTRST),
193 /* CAM2_RST */
194 PAD_CFG_GPO(GPP_E15, 1, PLTRST),
195 /* CAM2_PWR_EN */
196 PAD_CFG_GPO(GPP_E16, 1, PLTRST),
197
198 /* IMGCLKOUT */
199 PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
200 PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
201 PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
202 PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
203
204 /* BT_RF_KILL_N */
205 PAD_CFG_GPO(GPP_A13, 1, PLTRST),
206
207 /* D13 : WIFI_WAKE_N */
208 PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
209 /* WIFI RF KILL */
210 PAD_CFG_GPO(GPP_E3, 1, PLTRST),
211
212 /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
213 PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
214 /* F1 : CNV_BRI_RSP_BT_UART2_RXD */
215 PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
216 /* F2 : CNV_RGI_DT_BT_UART2_TXD */
217 PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
218 /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
219 PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
220 /* F4 : CNV_RF_RESET_R_N */
221 PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
222 /* F5 : MODEM_CLKREQ_R */
223 PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
224 /* TCH PAD Power EN */
225 PAD_CFG_GPO(GPP_F7, 1, PLTRST),
226
227 /* UART_BT_WAKE_N */
228 PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT),
229 };
230
variant_configure_gpio_pads(void)231 void variant_configure_gpio_pads(void)
232 {
233 gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
234 }
235
236 static const struct cros_gpio cros_gpios[] = {
237 CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
238 };
239 DECLARE_CROS_GPIOS(cros_gpios);
240