1chip soc/intel/xeon_sp/cpx 2 3 device cpu_cluster 0 on end 4 device domain 0 on 5 device pci 00.0 on end # Host bridge 6 device pci 04.0 on end 7 device pci 04.1 on end 8 device pci 04.2 on end 9 device pci 04.3 on end 10 device pci 04.4 on end 11 device pci 04.5 on end 12 device pci 04.6 on end 13 device pci 04.7 on end 14 device pci 05.0 on end 15 device pci 05.2 on end 16 device pci 05.4 on end 17 device pci 08.0 on end 18 device pci 08.1 on end 19 device pci 08.2 on end 20 device pci 11.0 on end 21 device pci 11.1 on end 22 device pci 11.5 on end 23 device pci 14.0 on end 24 device pci 16.0 on end 25 device pci 16.1 on end 26 device pci 16.4 on end 27 device pci 17.0 on end 28 device pci 1c.0 on end 29 device pci 1c.4 on end 30 device pci 1f.1 on end 31 device pci 1f.2 on end 32 device pci 1f.4 on end 33 device pci 1f.5 on end 34 device pci 1f.0 on # LPC/eSPI Interface 35 chip superio/common 36 device pnp 2e.0 on 37 chip superio/aspeed/ast2400 38 register "use_espi" = "1" 39 device pnp 2e.2 on # SUART1 40 io 0x60 = 0x3f8 41 irq 0x70 = 4 42 end 43 device pnp 2e.3 on # SUART2 44 io 0x60 = 0x2f8 45 irq 0x70 = 3 46 end 47 end 48 end 49 end 50 end 51 52 end 53end 54