1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <bootblock_common.h>
4 #include <device/pci_ops.h>
5 #include <southbridge/intel/i82801gx/i82801gx.h>
6 #include <northbridge/intel/pineview/pineview.h>
7 #include <superio/winbond/w83627thg/w83627thg.h>
8 #include <superio/winbond/common/winbond.h>
9
10 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
11
bootblock_mainboard_early_init(void)12 void bootblock_mainboard_early_init(void)
13 {
14 /* Disable Serial IRQ */
15 pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
16 /* Decode range */
17 pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
18 pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
19 | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN
20 | COMB_LPC_EN);
21
22 pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291);
23
24 winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
25 }
26
mb_pirq_setup(void)27 void mb_pirq_setup(void)
28 {
29 /* dev irq route register */
30 RCBA16(D31IR) = 0x0132;
31 RCBA16(D30IR) = 0x0146;
32 RCBA16(D29IR) = 0x0237;
33 RCBA16(D28IR) = 0x3201;
34 RCBA16(D27IR) = 0x0146;
35
36 /* Does not belong here, but is it needed? */
37 RCBA32(FD) |= FD_INTLAN;
38 }
39
get_mb_spd_addrmap(u8 * spd_addrmap)40 void get_mb_spd_addrmap(u8 *spd_addrmap)
41 {
42 spd_addrmap[0] = 0x50;
43 spd_addrmap[1] = 0x51;
44 }
45