1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef MAINBOARD_GPIO_H 4 #define MAINBOARD_GPIO_H 5 6 #include <soc/gpe.h> 7 #include <soc/gpio.h> 8 9 /* EC in RW */ 10 #define GPIO_EC_IN_RW GPP_C6 11 12 /* BIOS Flash Write Protect */ 13 #define GPIO_PCH_WP GPP_C23 14 15 /* Memory configuration board straps */ 16 #define GPIO_MEM_CONFIG_0 GPP_C12 17 #define GPIO_MEM_CONFIG_1 GPP_C13 18 #define GPIO_MEM_CONFIG_2 GPP_C14 19 #define GPIO_MEM_CONFIG_3 GPP_C15 20 21 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ 22 #define GPE_EC_WAKE GPE0_LAN_WAK 23 24 /* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ 25 #define GPE_WLAN_WAKE GPE0_DW0_16 26 27 /* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ 28 #define GPE_TOUCHPAD_WAKE GPE0_DW0_05 29 30 /* Input device interrupt configuration */ 31 #define TOUCHPAD_INT_L GPP_B3_IRQ 32 #define TOUCHSCREEN_INT_L GPP_E7_IRQ 33 #define MIC_INT_L GPP_F10_IRQ 34 35 /* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ 36 #define EC_SCI_GPI GPE0_DW2_16 37 #define EC_SMI_GPI GPP_E15 38 39 /* 40 * GPP_E3 is AUDIO_DB_ID. 41 * It is a dual purpose GPIO, used for Audio Daughter 42 * Board Identification & to control the shutdown mode pin 43 * of the Maxim amp. 44 */ 45 #define AUDIO_DB_ID GPP_E3 46 47 /* SD controller needs additional card detect GPIO to support RTD3 */ 48 #define GPIO_SD_CARD_DETECT GPP_A7 49 50 #ifndef __ACPI__ 51 /* Pad configuration in ramstage. */ 52 static const struct pad_config gpio_table[] = { 53 /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), 54 /* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), 55 /* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), 56 /* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), 57 /* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), 58 /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), 59 /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), 60 /* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), 61 /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), 62 /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), 63 /* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), 64 /* EC_HID_INT */ PAD_NC(GPP_A11, NONE), 65 /* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), 66 /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), 67 /* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), 68 /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), 69 /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), 70 /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), 71 /* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), 72 /* ISH_GP1 */ PAD_NC(GPP_A19, NONE), 73 /* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), 74 /* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), 75 /* GYRO_INT */ PAD_NC(GPP_A22, NONE), 76 /* ISH_GP5 */ PAD_NC(GPP_A23, NONE), 77 /* CORE_VID0 */ PAD_NC(GPP_B0, NONE), 78 /* CORE_VID1 */ PAD_NC(GPP_B1, NONE), 79 /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), 80 /* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), 81 /* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), 82 /* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ 83 /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), 84 /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), 85 /* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), 86 /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), 87 /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), 88 /* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), 89 /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), 90 /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), 91 /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), 92 /* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), 93 /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), 94 /* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), 95 /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), 96 /* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), 97 /* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), 98 /* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), 99 /* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), 100 /* SM1ALERT# */ PAD_NC(GPP_B23, NONE), 101 /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), 102 /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), 103 /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), 104 /* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), 105 /* SML0DATA */ PAD_NC(GPP_C4, NONE), 106 /* SML0ALERT# */ PAD_NC(GPP_C5, NONE), 107 /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), 108 /* USB_CTL */ PAD_NC(GPP_C7, NONE), 109 /* UART0_RXD */ PAD_NC(GPP_C8, NONE), 110 /* UART0_TXD */ PAD_NC(GPP_C9, NONE), 111 /* NFC_RST* */ PAD_NC(GPP_C10, NONE), 112 /* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, DN_20K, DEEP), 113 /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), 114 /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), 115 /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), 116 /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), 117 /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), 118 /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), 119 /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), 120 /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), 121 /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), 122 /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), 123 /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), 124 /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), 125 /* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), 126 /* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), 127 /* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), 128 /* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), 129 /* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), 130 /* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), 131 /* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), 132 /* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), 133 /* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), 134 /* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), 135 /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), 136 /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), 137 /* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), 138 /* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), 139 /* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), 140 /* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), 141 /* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), 142 /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), 143 /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), 144 /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), 145 /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), 146 /* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), 147 /* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), 148 /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), 149 /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), 150 /* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), 151 /* SSD_PEDET */ PAD_NC(GPP_E2, NONE), 152 /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), 153 /* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), 154 /* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), 155 /* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), 156 /* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), 157 /* SATALED# */ PAD_NC(GPP_E8, NONE), 158 /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), 159 /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), 160 /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), 161 /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), 162 /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), 163 /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), 164 /* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), 165 /* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), 166 /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), 167 /* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), 168 /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), 169 /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), 170 /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), 171 172 /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), 173 /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), 174 /* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), 175 /* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), 176 /* I2S2_TXD */ PAD_NC(GPP_F2, NONE), 177 /* I2S2_RXD */ PAD_NC(GPP_F3, NONE), 178 /* I2C2_SDA */ PAD_NC(GPP_F4, NONE), 179 /* I2C2_SCL */ PAD_NC(GPP_F5, NONE), 180 /* I2C3_SDA */ PAD_NC(GPP_F6, NONE), 181 /* I2C3_SCL */ PAD_NC(GPP_F7, NONE), 182 /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), 183 /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), 184 /* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), 185 /* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), 186 /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), 187 /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), 188 /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), 189 /* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), 190 /* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), 191 /* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), 192 /* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), 193 /* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), 194 /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), 195 /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), 196 /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), 197 /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), 198 /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), 199 /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), 200 /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), 201 /* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), 202 /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), 203 /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), 204 /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), 205 /* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), 206 /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), 207 /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), 208 /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), 209 /* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), 210 /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), 211 /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), 212 /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), 213 /* GPD7 */ PAD_NC(GPD7, NONE), 214 /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), 215 /* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), 216 /* PM_SLP_S5# */ PAD_NC(GPD10, NONE), 217 /* LANPHYC */ PAD_NC(GPD11, NONE), 218 }; 219 220 /* Early pad configuration in bootblock */ 221 static const struct pad_config early_gpio_table[] = { 222 /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ 223 /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), 224 /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ 225 /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), 226 }; 227 228 #endif 229 230 #endif 231