1FLASH 32M { 2 SI_ALL 9M { 3 SI_DESC 16K 4 SI_ME 5 } 6 SI_BIOS 23M { 7 RW_SECTION_A 7680K { 8 VBLOCK_A 8K 9 FW_MAIN_A(CBFS) 10 RW_FWID_A 64 11 } 12 # This section starts at the 16M boundary in SPI flash. 13 # MTL does not support a region crossing this boundary, 14 # because the SPI flash is memory-mapped into two non- 15 # contiguous windows. 16 RW_SECTION_B 7680K { 17 VBLOCK_B 8K 18 FW_MAIN_B(CBFS) 19 RW_FWID_B 64 20 } 21 RW_MISC 1M { 22 UNIFIED_MRC_CACHE(PRESERVE) 128K { 23 RECOVERY_MRC_CACHE 64K 24 RW_MRC_CACHE 64K 25 } 26 RW_ELOG(PRESERVE) 16K 27 RW_SHARED 16K { 28 SHARED_DATA 8K 29 VBLOCK_DEV 8K 30 } 31 # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. 32 # It is placed in the common `chromeos.fmd` file because it is only 4K and there 33 # is free space in the RW_MISC region that cannot be easily reclaimed because 34 # the RW_SECTION_B must start on the 16M boundary. 35 RW_SPD_CACHE(PRESERVE) 4K 36 RW_VPD(PRESERVE) 8K 37 RW_NVRAM(PRESERVE) 24K 38 } 39 RW_LEGACY(CBFS) 1M 40 RW_UNUSED 2M 41 # Make WP_RO region align with SPI vendor 42 # memory protected range specification. 43 WP_RO 4M { 44 RO_VPD(PRESERVE) 16K 45 46 RO_SECTION { 47 FMAP 2K 48 RO_FRID 64 49 GBB@4K 12K 50 COREBOOT(CBFS) 51 } 52 } 53 } 54} 55