1FLASH 32M { 2 SI_ALL 9M { 3 SI_DESC 16K 4 SI_EC 512K 5 SI_ME 6 } 7 SI_BIOS 23M { 8 RW_SECTION_A 7M { 9 VBLOCK_A 8K 10 FW_MAIN_A(CBFS) 11 RW_FWID_A 64 12 } 13 # This section starts at the 16M boundary in SPI flash. 14 # MTL does not support a region crossing this boundary, 15 # because the SPI flash is memory-mapped into two non- 16 # contiguous windows. 17 RW_SECTION_B 7M { 18 VBLOCK_B 8K 19 FW_MAIN_B(CBFS) 20 RW_FWID_B 64 21 } 22 RW_MISC 1M { 23 UNIFIED_MRC_CACHE(PRESERVE) 128K { 24 RECOVERY_MRC_CACHE 64K 25 RW_MRC_CACHE 64K 26 } 27 RW_ELOG(PRESERVE) 16K 28 RW_SHARED 16K { 29 SHARED_DATA 8K 30 VBLOCK_DEV 8K 31 } 32 # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. 33 # It is placed in the common `chromeos.fmd` file because it is only 4K and there 34 # is free space in the RW_MISC region that cannot be easily reclaimed because 35 # the RW_SECTION_B must start on the 16M boundary. 36 RW_SPD_CACHE(PRESERVE) 4K 37 RW_VPD(PRESERVE) 8K 38 RW_NVRAM(PRESERVE) 24K 39 } 40 RW_LEGACY(CBFS) 1M 41 RW_UNUSED 3M 42 # Make WP_RO region align with SPI vendor 43 # memory protected range specification. 44 WP_RO 4M { 45 RO_VPD(PRESERVE) 16K 46 RO_SECTION { 47 FMAP 2K 48 RO_FRID 64 49 GBB@4K 12K 50 COREBOOT(CBFS) 51 } 52 } 53 } 54} 55