1## SPDX-License-Identifier: GPL-2.0-only 2 3chip soc/intel/skylake 4 5 register "deep_s5_enable_ac" = "0" 6 register "deep_s5_enable_dc" = "0" 7 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" 8 9 # GPE configuration 10 # Note that GPE events called out in ASL code rely on this 11 # route. i.e. If this route changes then the affected GPE 12 # offset bits also need to be changed. 13 register "gpe0_dw0" = "GPP_B" 14 register "gpe0_dw1" = "GPP_D" 15 register "gpe0_dw2" = "GPP_E" 16 17 # FSP Configuration 18 register "DspEnable" = "1" 19 register "IoBufferOwnership" = "3" 20 register "SkipExtGfxScan" = "1" 21 22 # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch 23 # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s 24 register "PmConfigSlpS3MinAssert" = "0x02" 25 26 # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s 27 register "PmConfigSlpS4MinAssert" = "0x04" 28 29 # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s 30 register "PmConfigSlpSusMinAssert" = "0x03" 31 32 # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s 33 register "PmConfigSlpAMinAssert" = "0x03" 34 35 # VR Settings Configuration for 4 Domains 36 #+----------------+-----------+-----------+-------------+----------+ 37 #| Domain/Setting | SA | IA | GT Unsliced | GT | 38 #+----------------+-----------+-----------+-------------+----------+ 39 #| Psi1Threshold | 20A | 20A | 20A | 20A | 40 #| Psi2Threshold | 4A | 5A | 5A | 5A | 41 #| Psi3Threshold | 1A | 1A | 1A | 1A | 42 #| Psi3Enable | 1 | 1 | 1 | 1 | 43 #| Psi4Enable | 1 | 1 | 1 | 1 | 44 #| ImonSlope | 0 | 0 | 0 | 0 | 45 #| ImonOffset | 0 | 0 | 0 | 0 | 46 #| IccMax | 7A | 34A | 35A | 35A | 47 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 48 #+----------------+-----------+-----------+-------------+----------+ 49 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ 50 .vr_config_enable = 1, 51 .psi1threshold = VR_CFG_AMP(20), 52 .psi2threshold = VR_CFG_AMP(4), 53 .psi3threshold = VR_CFG_AMP(1), 54 .psi3enable = 1, 55 .psi4enable = 1, 56 .imon_slope = 0x0, 57 .imon_offset = 0x0, 58 .icc_max = VR_CFG_AMP(7), 59 .voltage_limit = 1520, 60 }" 61 62 register "domain_vr_config[VR_IA_CORE]" = "{ 63 .vr_config_enable = 1, 64 .psi1threshold = VR_CFG_AMP(20), 65 .psi2threshold = VR_CFG_AMP(5), 66 .psi3threshold = VR_CFG_AMP(1), 67 .psi3enable = 1, 68 .psi4enable = 1, 69 .imon_slope = 0x0, 70 .imon_offset = 0x0, 71 .icc_max = VR_CFG_AMP(34), 72 .voltage_limit = 1520, 73 }" 74 75 register "domain_vr_config[VR_GT_UNSLICED]" = "{ 76 .vr_config_enable = 1, 77 .psi1threshold = VR_CFG_AMP(20), 78 .psi2threshold = VR_CFG_AMP(5), 79 .psi3threshold = VR_CFG_AMP(1), 80 .psi3enable = 1, 81 .psi4enable = 1, 82 .imon_slope = 0x0, 83 .imon_offset = 0x0, 84 .icc_max = VR_CFG_AMP(35), 85 .voltage_limit = 1520, 86 }" 87 88 register "domain_vr_config[VR_GT_SLICED]" = "{ 89 .vr_config_enable = 1, 90 .psi1threshold = VR_CFG_AMP(20), 91 .psi2threshold = VR_CFG_AMP(5), 92 .psi3threshold = VR_CFG_AMP(1), 93 .psi3enable = 1, 94 .psi4enable = 1, 95 .imon_slope = 0x0, 96 .imon_offset = 0x0, 97 .icc_max = VR_CFG_AMP(35), 98 .voltage_limit = 1520, 99 }" 100 101 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V 102 103 # Must leave UART0 enabled or SD/eMMC will not work as PCI 104 105 register "SerialIoDevMode" = "{ 106 [PchSerialIoIndexI2C0] = PchSerialIoPci, 107 [PchSerialIoIndexI2C1] = PchSerialIoPci, 108 [PchSerialIoIndexI2C2] = PchSerialIoPci, 109 [PchSerialIoIndexI2C3] = PchSerialIoPci, 110 [PchSerialIoIndexI2C4] = PchSerialIoPci, 111 [PchSerialIoIndexI2C5] = PchSerialIoPci, 112 [PchSerialIoIndexSpi0] = PchSerialIoPci, 113 [PchSerialIoIndexSpi1] = PchSerialIoPci, 114 [PchSerialIoIndexUart0] = PchSerialIoPci, 115 [PchSerialIoIndexUart1] = PchSerialIoPci, 116 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, 117 }" 118 119 # PL2 override 25W 120 register "power_limits_config" = "{ 121 .tdp_pl2_override = 25, 122 }" 123 124 # Send an extra VR mailbox command for the PS4 exit issue 125 register "SendVrMbxCmd" = "2" 126 127 # Use default SD card detect GPIO configuration 128 #register "sdcard_cd_gpio" = "GPP_A7" 129 130 device domain 0 on 131 device ref igpu on end 132 device ref south_xhci on 133 register "SsicPortEnable" = "1" 134 135 register "usb2_ports" = "{ 136 [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ 137 [1] = USB2_PORT_MID(OC3), /* Touch Pad */ 138 [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ 139 [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ 140 [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ 141 [5] = USB2_PORT_MID(OC0), /* Front Panel */ 142 [6] = USB2_PORT_MID(OC0), /* Front Panel */ 143 [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ 144 [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ 145 [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ 146 [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ 147 [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ 148 [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ 149 [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ 150 }" 151 152 register "usb3_ports" = "{ 153 [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ 154 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ 155 [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ 156 [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ 157 [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ 158 [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ 159 [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ 160 [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ 161 [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ 162 [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ 163 }" 164 end 165 device ref thermal on end 166 device ref i2c0 on end 167 device ref i2c1 on end 168 device ref i2c2 on end 169 device ref i2c3 on end 170 device ref heci1 on end 171 device ref sata on 172 register "SataSalpSupport" = "1" 173 register "SataPortsEnable" = "{ 174 [0] = 1, 175 [1] = 1, 176 [2] = 1, 177 [3] = 1, 178 [4] = 1, 179 [5] = 1, 180 [6] = 1, 181 [7] = 1, 182 }" 183 end 184 device ref uart2 on end 185 device ref i2c5 on end 186 device ref i2c4 on end 187 device ref pcie_rp1 on end 188 device ref pcie_rp6 on 189 register "PcieRpEnable[5]" = "1" 190 register "PcieRpClkReqSupport[5]" = "1" 191 register "PcieRpClkReqNumber[5]" = "0" 192 end 193 device ref pcie_rp8 on 194 # x1 195 register "PcieRpEnable[7]" = "1" 196 register "PcieRpClkReqSupport[7]" = "1" 197 register "PcieRpClkReqNumber[7]" = "3" 198 end 199 device ref pcie_rp9 on 200 # x4 201 register "PcieRpEnable[8]" = "1" 202 register "PcieRpClkReqSupport[8]" = "1" 203 register "PcieRpClkReqNumber[8]" = "4" 204 end 205 device ref pcie_rp13 on 206 register "PcieRpEnable[12]" = "1" 207 register "PcieRpClkReqSupport[12]" = "1" 208 register "PcieRpClkReqNumber[12]" = "1" 209 end 210 device ref uart0 on end 211 device ref uart1 on end 212 device ref gspi0 on end 213 device ref gspi1 on end 214 device ref hda on end 215 device ref smbus on end 216 device ref lpc_espi on 217 register "serirq_mode" = "SERIRQ_CONTINUOUS" 218 end 219 device ref fast_spi on end 220 device ref gbe on end 221 end 222end 223