1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <acpi/acpi.h> 4 #include <cpu/x86/smm.h> 5 #include "ec.h" 6 7 #include <ec/google/chromeec/smm.h> 8 9 #include <soc/pm.h> 10 #include <soc/gpio.h> 11 12 #include "onboard.h" 13 14 /* The wake gpio is SUS_GPIO[0]. */ 15 #define WAKE_GPIO_EN SUS_GPIO_EN0 16 17 /* 18 * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that 19 * this includes the enable bits in the lower 16 bits. 20 */ mainboard_smi_gpi(uint32_t alt_gpio_smi)21void mainboard_smi_gpi(uint32_t alt_gpio_smi) 22 { 23 if (alt_gpio_smi & (1 << EC_SMI_GPI)) 24 chromeec_smi_process_events(); 25 } 26 mainboard_smi_sleep(uint8_t slp_typ)27void mainboard_smi_sleep(uint8_t slp_typ) 28 { 29 /* Disable USB charging if required */ 30 chromeec_set_usb_charge_mode(slp_typ); 31 32 switch (slp_typ) { 33 case ACPI_S3: 34 /* Enable wake pin in GPE block. */ 35 enable_gpe(WAKE_GPIO_EN); 36 break; 37 } 38 39 chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); 40 41 /* Set LPC lines to low power in S3/S5. */ 42 if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) 43 lpc_set_low_power(); 44 } 45 mainboard_smi_apmc(uint8_t apmc)46int mainboard_smi_apmc(uint8_t apmc) 47 { 48 chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); 49 return 0; 50 } 51