1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <southbridge/intel/lynxpoint/lp_gpio.h> 4 5 const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { 6 LP_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ 7 LP_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ 8 LP_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ 9 LP_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ 10 LP_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ 11 LP_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ 12 LP_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ 13 LP_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ 14 LP_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ 15 LP_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ 16 LP_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ 17 LP_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ 18 LP_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ 19 LP_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ 20 LP_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ 21 LP_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ 22 LP_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ 23 LP_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ 24 LP_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ 25 LP_GPIO_INPUT, /* 19: EC_IN_RW */ 26 LP_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ 27 LP_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ 28 LP_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ 29 LP_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ 30 LP_GPIO_OUT_LOW, /* 24: ME_PG_LED */ 31 LP_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ 32 LP_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ 33 LP_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ 34 LP_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ 35 LP_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ 36 LP_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ 37 LP_GPIO_NATIVE, /* 31: AC_PRESENT_R */ 38 LP_GPIO_NATIVE, /* 32: PM_CKRUN_N */ 39 LP_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ 40 LP_GPIO_INPUT, /* 34: ESATA_DET_N */ 41 LP_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ 42 LP_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ 43 LP_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ 44 LP_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ 45 LP_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ 46 LP_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ 47 LP_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ 48 LP_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ 49 LP_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ 50 LP_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ 51 LP_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ 52 LP_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ 53 LP_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ 54 LP_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ 55 LP_GPIO_INPUT, /* 49: COMBO_JD */ 56 LP_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ 57 LP_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ 58 LP_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ 59 LP_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ 60 LP_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ 61 LP_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ 62 LP_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ 63 LP_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ 64 LP_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ 65 LP_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ 66 LP_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ 67 LP_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ 68 LP_GPIO_NATIVE, /* 62: SUS_CK */ 69 LP_GPIO_NATIVE, /* 63: SLP_S5_R_N */ 70 LP_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ 71 LP_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ 72 LP_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ 73 LP_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ 74 LP_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ 75 LP_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ 76 LP_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ 77 LP_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ 78 LP_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ 79 LP_GPIO_NATIVE, /* 73: PCH_NOT_N */ 80 LP_GPIO_NATIVE, /* 74: SML1_DATA */ 81 LP_GPIO_NATIVE, /* 75: SML1_CK */ 82 LP_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ 83 LP_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ 84 LP_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ 85 LP_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ 86 LP_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ 87 LP_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ 88 LP_GPIO_NATIVE, /* 82: H_RCIN_N */ 89 LP_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ 90 LP_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ 91 LP_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ 92 LP_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ 93 LP_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ 94 LP_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ 95 LP_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ 96 LP_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ 97 LP_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ 98 LP_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ 99 LP_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ 100 LP_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ 101 LP_GPIO_END 102 }; 103