1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootblock_common.h>
4 #include <device/pci_def.h>
5 #include <device/pci_ops.h>
6 #include <intelblocks/lpc_lib.h>
7 #include <intelblocks/pcr.h>
8 #include <soc/intel/common/block/lpc/lpc_def.h>
9 #include <soc/pci_devs.h>
10 #include <soc/pcr_ids.h>
11 #include <superio/aspeed/ast2400/ast2400.h>
12 #include <superio/aspeed/common/aspeed.h>
13
14 #define ASPEED_SIO_PORT 0x2E
15 #define PCR_DMI_LPCIOD 0x2770
16 #define PCR_DMI_LPCIOE 0x2774
17
bootblock_mainboard_early_init(void)18 void bootblock_mainboard_early_init(void)
19 {
20 /*
21 * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports,
22 * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
23 * For ArcherCity CRB, only SUART1 is used.
24 */
25 uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
26 uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
27
28 /* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */
29 pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
30 /* LPC I/O enable: com1 and com2 */
31 pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
32
33 /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
34 pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
35 pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
36
37 const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
38 aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
39 }
40