1FLASH@0xff400000 0xc00000 { 2 SI_ALL@0x0 0x500000 { 3 SI_DESC@0x0 0x1000 4 SI_GBE@0x1000 0x2000 5 SI_ME 6 } 7 SI_BIOS@0x500000 0x700000 { 8 RW_SECTION_A 0x280000 { 9 VBLOCK_A 0x10000 10 FW_MAIN_A(CBFS) 11 RW_FWID_A 0x40 12 } 13 RW_SECTION_B 0x280000 { 14 VBLOCK_B 0x10000 15 FW_MAIN_B(CBFS) 16 RW_FWID_B 0x40 17 } 18 UNIFIED_MRC_CACHE@0x500000 0x20000 { 19 RECOVERY_MRC_CACHE@0x0 0x10000 20 RW_MRC_CACHE@0x10000 0x10000 21 } 22 RW_VPD(PRESERVE) 0x1000 23 SMMSTORE(PRESERVE)@0x521000 0x40000 24 RW_NVRAM(PRESERVE)@0x561000 0x2000 25 26 WP_RO { 27 FMAP 0x800 28 RO_FRID 0x40 29 RO_PADDING 0x7c0 30 RO_VPD(PRESERVE) 0x1000 31 GBB 0x1e000 32 COREBOOT(CBFS) 33 } 34 } 35} 36