1# PCEngines 2Gb 1333 2 3# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down 4# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage 5# bits[3:0]: 1 = 128 SPD Bytes Used 6# bits[6:4]: 1 = 256 SPD Bytes Total 7# bit7 : 0 = CRC covers bytes 0 ~ 128 801 9 10# 1 SPD Revision 11# 0x13 = Revision 1.3 1213 13 14# 2 Key Byte / DRAM Device Type 15# bits[7:0]: 0x0b = DDR3 SDRAM 160B 17 18# 3 Key Byte / Module Type 19# bits[3:0]: 3 = SO-DIMM 20# bits[3:0]: 8 = 72b-SO-DIMM 21# bits[7:4]: reserved 2203 23 24# 4 SDRAM CHIP Density and Banks 25# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip 26# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip 27# bits[6:4]: 0 = 3 (8 banks) 28# bit7 : reserved 2903 30 31# 5 SDRAM Addressing 32# bits[2:0]: 1 = 10 Column Address Bits 33# bits[5:3]: 4 = 16 Row Address Bits 34# bits[5:3]: 3 = 15 Row Address Bits 35# bits[5:3]: 2 = 14 Row Address Bits 36# bits[7:6]: reserved 3719 38 39# 6 Module Nominal Voltage, VDD 40# bit0 : 0 = 1.5 V operable 41# bit1 : 0 = NOT 1.35 V operable 42# bit2 : 0 = NOT 1.25 V operable 43# bits[7:3]: reserved 4400 45 46# 7 Module Organization 47# bits[2:0]: 1 = 8 bits 48# bits[2:0]: 2 = 16 bits 49# bits[5:3]: 0 = 1 Rank 50# bits[7:6]: reserved 5101 52 53# 8 Module Memory Bus Width 54# bits[2:0]: 3 = Primary bus width is 64 bits 55# bits[4:3]: 0 = 0 bits (no bus width extension) 56# bits[4:3]: 1 = 8 bits (for ECC) 57# bits[7:5]: reserved 5803 59 60# 9 Fine Timebase (FTB) Dividend / Divisor 61# bits[3:0]: 0x02 divisor 62# bits[7:4]: 0x05 dividend 63# 5 / 2 = 2.5ps 6452 65 66# 10 Medium Timebase (MTB) Dividend 67# 11 Medium Timebase (MTB) Divisor 68# 1 / 8 = .125 ns 6901 08 70 71# 12 SDRAM Minimum Cycle Time (tCKmin) 72# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) 73# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) 74# 0x0c = tCKmin of 1.5 ns = in multiples of MTB 750C 76 77# 13 Reserved 7800 79 80# 14 CAS Latencies Supported, Least Significant Byte 81# 15 CAS Latencies Supported, Most Significant Byte 82# Cas Latencies of 11 - 5 are supported 837E 00 84 85# 16 Minimum CAS Latency Time (tAAmin) 86# 0x6C = 13.5ns - DDR3-1333 87# 0x69 = 13.125 ns - DDR3-1333 8869 89 90# 17 Minimum Write Recovery Time (tWRmin) 91# 0x78 = tWR of 15ns - All DDR3 speed grades 9278 93 94# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) 95# 0x6E = 13.5ns - DDR3-1333 96# 0x69 = 13.125 ns - DDR3-1333 9769 98 99# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) 100# 0x30 = 6.0ns 101# 0x38 = 7.0ns 102# 0x3C = 7.5ns 10330 104 105# 20 Minimum Row Precharge Delay Time (tRPmin) 106# 0x6C = 13.5ns - 107# 0x69 = 13.125 ns - DDR3-1333 10869 109 110# 21 Upper Nibbles for tRAS and tRC 111# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) 112# bits[7:4]: tRC most significant nibble = 1 (see byte 23) 11311 114 115# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB 116# 0x120 = 36ns - DDR3-1333 (see byte 21) 117# 0x120 = 36ns - DDR3 11820 119 120# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB 121# 0x289 = 49.125ns - DDR3-1333 12289 123 124# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB 125# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB 126# 0x500 = 160ns - for 2 Gigabit chips 127# 0x820 = 260ns - for 4 Gigabit chips 12800 05 129 130# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) 131# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins 1323C 133 134# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) 135# 0x3c = 7.5ns - All DDR3 SDRAM speed bins 1363C 137 138# 28 Upper Nibble for tFAWmin 139# 29 Minimum Four Activate Window Delay Time (tFAWmin) 140# 0x00F0 = 30ns - DDR3-1333, 1 KB page size 14100 F0 142 143# 30 SDRAM Optional Feature 144# bit0 : 1= RZQ/6 supported 145# bit1 : 1 = RZQ/7 supported 146# bits[6:2]: reserved 147# bit7 : 1 = DLL Off mode supported 14883 149 150# 31 SDRAM Thermal and Refresh Options 151# bit0 : 1 = Temp up to 95c supported 152# bit1 : 0 = 85-95c uses 2x refresh rate 153# bit2 : 1 = Auto Self Refresh supported 154# bit3 : 0 = no on die thermal sensor 155# bits[6:4]: reserved 156# bit7 : 0 = partial self refresh supported 15701 158 159# 32 Module Thermal Sensor 160# 0 = Thermal sensor not incorporated onto this assembly 16100 162 163# 33 SDRAM Device Type 164# bits[1:0]: 0 = Signal Loading not specified 165# bits[3:2]: reserved 166# bits[6:4]: 0 = Die count not specified 167# bit7 : 0 = Standard Monolithic DRAM Device 16800 169 170# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) 17100 172 173# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) 17400 175 176# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 17700 178 179# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) 18000 181 182# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) 18300 184 185# 39 40 (reserved) 18600 00 187 188# 41 tMAW, MAC 189# 8K*tREFI / 200k 19086 191 192# 42 - 47 (reserved) 19300 00 00 00 00 00 194 195# 48 - 55 (reserved) 19600 00 00 00 00 00 00 00 197 198# 56 - 59 (reserved) 19900 00 00 00 200 201# 60 Raw Card Extension, Module Nominal Height 202# bits[4:0]: 0 = <= 15mm tall 203# bits[7:5]: 0 = raw card revision 0-3 20400 205 206# 61 Module Maximum Thickness 207# bits[3:0]: 0 = thickness front <= 1mm 208# bits[7:4]: 0 = thinkness back <= 1mm 20900 210 211# 62 Reference Raw Card Used 212# bits[4:0]: 0 = Reference Raw card A used 213# bits[6:5]: 0 = revision 0 214# bit7 : 0 = Reference raw cards A through AL 215# revision B4 21661 217 218# 63 Address Mapping from Edge Connector to DRAM 219# bit0 : 0 = standard mapping (not mirrored) 220# bits[7:1]: reserved 22100 222 223# 64 - 71 (reserved) 22400 00 00 00 00 00 00 00 225 226# 72 - 79 (reserved) 22700 00 00 00 00 00 00 00 228 229# 80 - 87 (reserved) 23000 00 00 00 00 00 00 00 231 232# 88 - 95 (reserved) 23300 00 00 00 00 00 00 00 234 235# 96 - 103 (reserved) 23600 00 00 00 00 00 00 00 237 238# 104 - 111 (reserved) 23900 00 00 00 00 00 00 00 240 241# 112 - 116 (reserved) 24200 00 00 00 00 243 244# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code 245# 0x0001 = AMD 24600 01 247 248# 119 Module ID: Module Manufacturing Location - OEM specified 24900 250 251# 120 Module ID: Module Manufacture Year in BCD 252# 0x15 = 2015 25315 254 255# 121 Module ID: Module Manufacture week 256# 0x44 = 44th week 25744 258 259# 122 - 125: Module Serial Number 26000 00 00 00 261 262# 126 - 127: Cyclical Redundancy Code 263b6 73 264