1# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix 2 3# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down 4# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage 5# bits[3:0]: 1 = 128 SPD Bytes Used 6# bits[6:4]: 1 = 256 SPD Bytes Total 7# bit7 : 0 = CRC covers bytes 0 ~ 128 801 9 10# 1 SPD Revision - 11# 0x13 = Revision 1.3 1213 13# 2 Key Byte / DRAM Device Type 14# bits[7:0]: 0x0b = DDR3 SDRAM 150B 16 17# 3 Key Byte / Module Type 18# bits[3:0]: 3 = SO-DIMM 19# bits[3:0]: 8 = 72b-SO-DIMM 20# bits[7:4]: reserved 2108 22 23# 4 SDRAM CHIP Density and Banks 24# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip 25# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip 26# bits[6:4]: 0 = 3 (8 banks) 27# bit7 : reserved 2804 29 30# 5 SDRAM Addressing 31# bits[2:0]: 1 = 10 Column Address Bits 32# bits[5:3]: 4 = 16 Row Address Bits 33# bits[5:3]: 3 = 15 Row Address Bits 34# bits[5:3]: 2 = 14 Row Address Bits 35# bits[7:6]: reserved 3621 37 38# 6 Module Nominal Voltage, VDD 39# bit0 : 0 = 1.5 V operable 40# bit1 : 0 = NOT 1.35 V operable 41# bit2 : 0 = NOT 1.25 V operable 42# bits[7:3]: reserved 4300 44 45# 7 Module Organization 46# bits[2:0]: 1 = 8 bits 47# bits[2:0]: 2 = 16 bits 48# bits[5:3]: 0 = 1 Rank 49# bits[7:6]: reserved 5001 51 52# 8 Module Memory Bus Width 53# bits[2:0]: 3 = Primary bus width is 64 bits 54# bits[4:3]: 0 = 0 bits (no bus width extension) 55# bits[4:3]: 1 = 8 bits (for ECC) 56# bits[7:5]: reserved 570B 58 59# 9 Fine Timebase (FTB) Dividend / Divisor 60# bits[3:0]: 0x02 divisor 61# bits[7:4]: 0x05 dividend 62# 5 / 2 = 2.5 ps 6352 64 65# 10 Medium Timebase (MTB) Dividend 66# 11 Medium Timebase (MTB) Divisor 67# 1 / 8 = .125 ns 6801 08 69 70# 12 SDRAM Minimum Cycle Time (tCKmin) 71# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) 72# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) 73# 0x0c = tCKmin of 1.5 ns = in multiples of MTB 740C 75 76# 13 Reserved 7700 78 79# 14 CAS Latencies Supported, Least Significant Byte 80# 15 CAS Latencies Supported, Most Significant Byte 81# Cas Latencies of 11 - 5 are supported 827E 00 83 84# 16 Minimum CAS Latency Time (tAAmin) 85# 0x6C = 13.5ns - DDR3-1333 86# 0x69 = 13.125 ns - DDR3-1333 8769 88 89# 17 Minimum Write Recovery Time (tWRmin) 90# 0x78 = tWR of 15ns - All DDR3 speed grades 9178 92 93# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) 94# 0x6E = 13.5ns - DDR3-1333 95# 0x69 = 13.125 ns - DDR3-1333 9669 97 98# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) 99# 0x30 = 6ns 100# 0x38 = 7.0ns 101# 0x3C = 7.5ns 10230 103 104# 20 Minimum Row Precharge Delay Time (tRPmin) 105# 0x6C = 13.5ns - 106# 0x69 = 13.125 ns - DDR3-1333 10769 108 109# 21 Upper Nibbles for tRAS and tRC 110# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) 111# bits[7:4]: tRC most significant nibble = 1 (see byte 23) 11211 113 114# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB 115# 0x120 = 36ns - DDR3-1333 (see byte 21) 116# 0x120 = 36ns - DDR3 11720 118 119# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB 120# 0x28C = 49.5ns - DDR3-1333 121# 0x289 = 49.125ns - DDR3-1333 12289 123 124# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB 125# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB 126# 0x500 = 160ns - for 2 Gigabit chips 127# 0x820 = 260ns - for 4 Gigabit chips 12820 08 129 130# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) 131# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins 1323C 133 134# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) 135# 0x3c = 7.5ns - All DDR3 SDRAM speed bins 1363C 137 138# 28 Upper Nibble for tFAWmin 139# 29 Minimum Four Activate Window Delay Time (tFAWmin) 140# 0x00F0 = 30ns - DDR3-1333, 1 KB page size 14100 F0 142 143# 30 SDRAM Optional Feature 144# bit0 : 1= RZQ/6 supported 145# bit1 : 1 = RZQ/7 supported 146# bits[6:2]: reserved 147# bit7 : 1 = DLL Off mode supported 14883 149 150# 31 SDRAM Thermal and Refresh Options 151# bit0 : 1 = Temp up to 95c supported 152# bit1 : 0 = 85-95c uses 2x refresh rate 153# bit2 : 1 = Auto Self Refresh supported 154# bit3 : 0 = no on die thermal sensor 155# bits[6:4]: reserved 156# bit7 : 0 = partial self refresh supported 15701 158 159# 32 Module Thermal Sensor 160# 0 = Thermal sensor not incorporated onto this assembly 16100 162 163# 33 SDRAM Device Type 164# bits[1:0]: 0 = Signal Loading not specified 165# bits[3:2]: reserved 166# bits[6:4]: 0 = Die count not specified 167# bit7 : 0 = Standard Monolithic DRAM Device 16800 169 170# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) 17100 172# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) 17300 174# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 17500 176# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) 17700 178# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) 17900 180 181# 39 40 (reserved) 18200 00 183 184# 41 tMAW, MAC 185# 8K*tREFI / 200k 18686 187 188# 42 - 47 (reserved) 18900 00 00 00 00 00 190 191# 48 - 55 (reserved) 19200 00 00 00 00 00 00 00 193 194# 56 - 59 (reserved) 19500 00 00 00 196 197# 60 Raw Card Extension, Module Nominal Height 198# bits[4:0]: 0 = <= 15mm tall 199# bits[7:5]: 0 = raw card revision 0-3 20000 201 202# 61 Module Maximum Thickness 203# bits[3:0]: 0 = thickness front <= 1mm 204# bits[7:4]: 0 = thinkness back <= 1mm 20500 206 207# 62 Reference Raw Card Used 208# bits[4:0]: 0 = Reference Raw card A used 209# bits[6:5]: 0 = revision 0 210# bit7 : 0 = Reference raw cards A through AL 211# revision B4 21261 213 214# 63 Address Mapping from Edge Connector to DRAM 215# bit0 : 0 = standard mapping (not mirrored) 216# bits[7:1]: reserved 21700 218 219# 64 - 71 (reserved) 22000 00 00 00 00 00 00 00 221 222# 72 - 79 (reserved) 22300 00 00 00 00 00 00 00 224 225# 80 - 87 (reserved) 22600 00 00 00 00 00 00 00 227 228# 88 - 95 (reserved) 22900 00 00 00 00 00 00 00 230 231# 96 - 103 (reserved) 23200 00 00 00 00 00 00 00 233 234# 104 - 111 (reserved) 23500 00 00 00 00 00 00 00 236 237# 112 - 116 (reserved) 23800 00 00 00 00 239 240# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code 241# 0x0001 = AMD 24200 01 243 244# 119 Module ID: Module Manufacturing Location - oem specified 24500 246 247# 120 Module ID: Module Manufacture Year in BCD 248# 0x15 = 2015 249# 121 Module ID: Module Manufacture week 250# 0x44 = 44th week 25115 44 252 253# 122 - 125: Module Serial Number 25400 00 00 00 255 256# 126 - 127: Cyclical Redundancy Code 25767 94 258