1chip soc/intel/alderlake 2 3 # GPE configuration 4 # Note that GPE events called out in ASL code rely on this 5 # route. i.e. If this route changes then the affected GPE 6 # offset bits also need to be changed. 7 register "pmc_gpe0_dw0" = "GPP_B" 8 register "pmc_gpe0_dw1" = "GPP_D" 9 register "pmc_gpe0_dw2" = "GPP_E" 10 11 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f 12 register "gen1_dec" = "0x00fc0801" 13 register "gen2_dec" = "0x000c0201" 14 # EC memory map range is 0x900-0x9ff 15 register "gen3_dec" = "0x00fc0901" 16 # EC EMI 0 range is 0xc00 - 0xc0f 17 register "gen4_dec" = "0x000c0c01" 18 19 # SaGv Configuration 20 register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" 21 22 # Disable S0ix 23 register "s0ix_enable" = "0" 24 25 # Display configuration (4 DPs) 26 register "ddi_ports_config" = "{ 27 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, 28 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, 29 [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, 30 [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, 31 }" 32 33 # Acoustic settings 34 register "acoustic_noise_mitigation" = "1" 35 register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4" 36 register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4" 37 register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" 38 register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" 39 40 # USB configuration 41 register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" 42 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" 43 register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" 44 register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" 45 register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" 46 register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" 47 register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" 48 register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" 49 50 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" 51 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" 52 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" 53 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" 54 55 register "ibecc.enable" = "CONFIG(ATLAS_ENABLE_IBECC)" 56 register "ibecc.mode" = "CONFIG(ATLAS_ENABLE_IBECC) ? IBECC_MODE_ALL : IBECC_MODE_NONE" 57 58 register "sata_salp_support" = "1" 59 60 register "sata_ports_enable" = "{ 61 [0] = 1, 62 [1] = 1, 63 }" 64 65 register "sata_ports_dev_slp" = "{ 66 [0] = 1, 67 [1] = 1, 68 }" 69 70 register "serial_io_uart_mode" = "{ 71 [PchSerialIoIndexUART0] = PchSerialIoSkipInit, 72 [PchSerialIoIndexUART1] = PchSerialIoPci, 73 [PchSerialIoIndexUART2] = PchSerialIoDisabled, 74 }" 75 76 # Clock source 0 is shared between PCH RP 5, 6, 7, 8, 9 and CPU RP 1, 2, 3 77 # Clock source 0 is therefore marked as FREE_RUNNING 78 # Set PCIE_RP_CLK_SRC_UNUSED on the root ports using clock source 0 so that 79 # we don't get a warning at boot about a missing clock definition. 80 register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" 81 82 register "pch_pcie_rp[PCH_RP(5)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" 83 register "pch_pcie_rp[PCH_RP(6)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" 84 register "pch_pcie_rp[PCH_RP(7)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" 85 register "pch_pcie_rp[PCH_RP(8)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" 86 register "pch_pcie_rp[PCH_RP(9)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" # UFS or general purpose RP 87 88 register "pch_pcie_rp[PCH_RP(5)].pcie_rp_aspm" = "ASPM_DISABLE" 89 register "pch_pcie_rp[PCH_RP(6)].pcie_rp_aspm" = "ASPM_DISABLE" 90 register "pch_pcie_rp[PCH_RP(7)].pcie_rp_aspm" = "ASPM_DISABLE" 91 register "pch_pcie_rp[PCH_RP(8)].pcie_rp_aspm" = "ASPM_DISABLE" 92 register "pch_pcie_rp[PCH_RP(9)].pcie_rp_aspm" = "ASPM_DISABLE" 93 94 register "pch_pcie_rp[PCH_RP(5)].PcieRpL1Substates" = "L1_SS_DISABLED" 95 register "pch_pcie_rp[PCH_RP(6)].PcieRpL1Substates" = "L1_SS_DISABLED" 96 register "pch_pcie_rp[PCH_RP(7)].PcieRpL1Substates" = "L1_SS_DISABLED" 97 register "pch_pcie_rp[PCH_RP(8)].PcieRpL1Substates" = "L1_SS_DISABLED" 98 register "pch_pcie_rp[PCH_RP(9)].PcieRpL1Substates" = "L1_SS_DISABLED" 99 100 # Enable PCIe-to-i225 bridge using clk 1 101 #TODO set clk_req, once it's connected on atlas. clk_req now defaults to 0, 102 # because using 0xFF (unused) would trigger a bug. 103 register "pch_pcie_rp[PCH_RP(10)]" = "{ 104 .clk_src = 1, 105 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, 106 .pcie_rp_aspm = ASPM_AUTO, 107 }" 108 109 device domain 0 on 110 device ref pcie5_0 on 111 register "cpu_pcie_rp[CPU_RP(2)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED" 112 register "cpu_pcie_rp[CPU_RP(2)].pcie_rp_aspm" = "ASPM_AUTO" 113 register "cpu_pcie_rp[CPU_RP(2)].PcieRpL1Substates" = "L1_SS_DISABLED" 114 end 115 device ref igpu on end 116 # without DDT enabled, edk2 doesn't even finish (TODO) 117 device ref dtt on end 118 device ref pcie4_0 on 119 register "cpu_pcie_rp[CPU_RP(1)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED" 120 register "cpu_pcie_rp[CPU_RP(1)].pcie_rp_aspm" = "ASPM_DISABLE" 121 register "cpu_pcie_rp[CPU_RP(1)].PcieRpL1Substates" = "L1_SS_DISABLED" 122 end 123 device ref pcie4_1 on 124 register "cpu_pcie_rp[CPU_RP(3)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED" 125 register "cpu_pcie_rp[CPU_RP(3)].pcie_rp_aspm" = "ASPM_DISABLE" 126 register "cpu_pcie_rp[CPU_RP(3)].PcieRpL1Substates" = "L1_SS_DISABLED" 127 end 128 # TODO try enabling crashlog 129 device ref crashlog on end 130 device ref ish on end 131 device ref ufs off end 132 device ref tcss_xhci on end 133 device ref xhci on end 134 device ref heci1 on end 135 device ref sata on end 136 # pcie_rp[1-4] is used for USB 137 device ref pcie_rp5 on end 138 device ref pcie_rp6 on end 139 device ref pcie_rp7 on end 140 device ref pcie_rp8 on end 141 device ref pcie_rp9 on end 142 device ref pcie_rp10 on end 143 # pcie_rp[11-12] is used for SATA 144 device ref uart0 on end 145 device ref uart1 on end 146 device ref pch_espi on 147 chip drivers/pc80/tpm 148 device pnp 0c31.0 on end 149 end 150 end 151 device ref p2sb on end 152 device ref hda on end 153 device ref smbus on end 154 end 155end 156