1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <types.h>
4
5 #include "gpio.h"
6
7 /*
8 * Pad configuration in ramstage
9 * Intel Client PCIe* controller expects each device should drive the SRCCLKREQ#.
10 * If the GPIO is set to native mode for a device, which do not support SRCCLKREQ#,
11 * then during RTD3 exit link would not be established. Because controller samples
12 * the SRCCLKREQ# before detecting the device and break L1 as the system might enter L1SS
13 * as controller detects SRCCLKREQ# as de-asserted.
14 * As a workaround the Pins must not be configured in Native Mode (CLKREQ mode).
15 * Therefore here they are not configured at all.
16 * source: 689882 (intel document ID)
17 *
18 * So apparently hardware doesn't sample SRCCLKREQ Pin if it's not configured as such.
19 * That workaround suggestion however also brought a patch to FSP, which in
20 * turn causes the same Bug (even if SRCLKREQ are not configured). Usually
21 * in order to make use of root port power saving features (e.g.
22 * clock gating), the Root port must either be disabled or a CLKREQ Pin
23 * must be configured. The patch however removed that check before
24 * enabling power management for the rootport.
25 * Workaround (until FSP is fixed):
26 *
27 * Workaround:
28 * pretend to FSP that the rootports have a CLKREQ Pin attached, by supplying them in the
29 * FSP UPDs. That will cause FSP to configure the Pin or CLKREQ and enable power
30 * management for said rootport, but it will not crash on L1 entry/exit. That has been done
31 * on the Atlas board (as workaround) for a short period of time (before applying FSP Fix)
32 * like this:
33 * - memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // RP 5 (the rootport you want to fix)
34 * - memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; // e.g. choose a clkreq pin that is not routed out
35 */
36 static const struct pad_config gpio_table[] = {
37 /*
38 * Do not program virtual wire CPU CLKREQ pins, since CLKREQ of cpu rootports are not
39 * connected on this mainboard.
40 */
41
42 /* ------- GPIO Group GPP_A ------- */
43 PAD_NC(GPP_A7, NONE),
44 PAD_CFG_GPI(GPP_A8, NONE, DEEP), // HSID_0 / CLKREQ 7
45 //PAD_NC(GPP_A12, NONE), CLKREQ 9B ???
46 PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // USB_2_3_OC_N
47 PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // USB_4_5_OC_N
48 PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_6_7_OC_N
49 PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // DP1_HPD
50 PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), // DP2_HPD
51 PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), // DP3_HPD
52 PAD_NC(GPP_A23, NONE), // ESPI_CS1
53
54 /* ------- GPIO Group GPP_B ------- */
55 PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // AUX_VID0
56 PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // AUX_VID1
57 PAD_NC(GPP_B5, NONE),
58 PAD_NC(GPP_B6, NONE),
59 PAD_NC(GPP_B7, NONE),
60 PAD_NC(GPP_B8, NONE),
61 PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SATA_SPKR_N
62 PAD_NC(GPP_B15, NONE),
63 PAD_NC(GPP_B16, NONE),
64 PAD_NC(GPP_B17, NONE),
65 PAD_NC(GPP_B18, NONE),
66 PAD_NC(GPP_B23, NONE), // SML1_ALERT
67
68 /* ------- GPIO Group GPP_C ------- */
69 PAD_NC(GPP_C5, NONE), // SML0_ALERT
70 PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK
71 PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA
72
73 /* ------- GPIO Group GPP_D ------- */
74 PAD_NC(GPP_D0, NONE),
75 PAD_NC(GPP_D1, NONE),
76 PAD_NC(GPP_D2, NONE),
77 PAD_NC(GPP_D3, NONE),
78 //PAD_NC(GPP_D5, NONE), CLKREQ 0
79 //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // PHY0_CLKREQ / CLKREQ 1
80 //PAD_NC(GPP_D7, NONE), CLKREQ 2
81 //PAD_NC(GPP_D8, NONE), CLKREQ 3
82 PAD_NC(GPP_D9, NONE),
83 PAD_NC(GPP_D10, NONE),
84 PAD_NC(GPP_D11, NONE),
85 PAD_NC(GPP_D12, NONE),
86 PAD_NC(GPP_D13, NONE),
87 PAD_NC(GPP_D14, NONE),
88 PAD_NC(GPP_D15, NONE),
89 PAD_NC(GPP_D16, NONE),
90 PAD_NC(GPP_D19, NONE),
91
92 /* ------- GPIO Group GPP_E ------- */
93 //PAD_NC(GPP_E0, NONE), CLKREQ 9
94 PAD_NC(GPP_E1, NONE),
95 PAD_NC(GPP_E2, NONE),
96 PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* TPM INT (todo: check) */
97 PAD_NC(GPP_E4, NONE),
98 PAD_NC(GPP_E5, NONE),
99 PAD_CFG_GPI(GPP_E6, NONE, DEEP),
100 PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE), /* EC SMI# */
101 PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* PERST_CB_RESET_N */
102 PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_0_1_OC_N */
103 PAD_NC(GPP_E10, NONE),
104 PAD_NC(GPP_E11, NONE),
105 PAD_NC(GPP_E12, NONE),
106 PAD_NC(GPP_E13, NONE),
107 PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP0_HPD (VGA_RED) */
108 PAD_NC(GPP_E15, NONE),
109 //PAD_NC(GPP_E16, NONE), CLKREQ 8
110 PAD_NC(GPP_E17, NONE),
111 PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DP3_DDC_CTRLCLK */
112 PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DP3_DDC_CTRLDATA */
113 PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DP2_DDC_CTRLCLK */
114 PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DP2_DDC_CTRLDATA */
115 PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* DP0_DDC_CTRLCLK */
116 PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DP0_DDC_CTRLDATA */
117
118 /* ------- GPIO Group GPP_F ------- */
119 PAD_NC(GPP_F0, NONE),
120 PAD_NC(GPP_F1, NONE),
121 PAD_CFG_GPI(GPP_F2, NONE, DEEP),
122 PAD_NC(GPP_F3, NONE),
123 PAD_NC(GPP_F5, NONE),
124 PAD_CFG_GPO(GPP_F9, 1, DEEP), /* EC_SLP_S0_CS_N */
125 PAD_NC(GPP_F11, NONE),
126 PAD_CFG_GPI(GPP_F12, NONE, DEEP),
127 PAD_CFG_GPI(GPP_F13, NONE, DEEP),
128 PAD_NC(GPP_F17, NONE),
129 PAD_NC(GPP_F18, NONE),
130 PAD_CFG_GPI(GPP_F19, NONE, DEEP), // HSID_1 / CLKREQ 6
131 PAD_NC(GPP_F20, NONE),
132 PAD_NC(GPP_F21, NONE),
133 PAD_CFG_GPO(GPP_F22, 1, DEEP), /* PERST_PHY0_N */
134
135 /* ------- GPIO Group GPP_H ------- */
136 PAD_NC(GPP_H4, NONE),
137 PAD_NC(GPP_H5, NONE),
138 PAD_NC(GPP_H6, NONE),
139 PAD_NC(GPP_H7, NONE),
140 PAD_NC(GPP_H12, NONE),
141 PAD_NC(GPP_H13, NONE),
142 PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */
143 PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */
144 PAD_CFG_GPI(GPP_H19, NONE, DEEP), // HSID_3 / CLKREQ 4
145 PAD_CFG_GPI(GPP_H23, NONE, DEEP), // HSID_2 / CLKREQ 5
146
147 /* ------- GPIO Group GPP_R ------- */
148 PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BCLK
149 PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), // HDA_SYNC
150 PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), // HDA_SDOUT
151 PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), // HDA_SDIN0
152 PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST
153 PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1), // HDA_SDIN1
154 PAD_NC(GPP_R6, NONE),
155 PAD_NC(GPP_R7, NONE),
156
157 /* ------- GPIO Group GPP_T ------- */
158 PAD_NC(GPP_T2, NONE),
159 PAD_NC(GPP_T3, NONE),
160
161 /* ------- GPIO Group GPD ------- */
162 PAD_NC(GPD8, NONE), /* SUSCLK */
163 PAD_CFG_GPO(GPD11, 1, PLTRST), /* LAN_DISABLE_N */
164 };
165
configure_gpio_pads(void)166 void configure_gpio_pads(void)
167 {
168 gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
169 }
170