1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootblock_common.h>
4 #include <arch/io.h>
5 #include <device/pnp_ops.h>
6 #include <superio/smsc/lpc47n227/lpc47n227.h>
7
8 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
9
bootblock_mainboard_early_init(void)10 void bootblock_mainboard_early_init(void)
11 {
12 /* Original settings:
13 idx 30 31 32 33 34 35 36 37 38 39
14 val 60 00 00 40 00 ff 00 e0 00 80
15 def 00 00 00 00 00 00 00 00 00 80
16
17 Values:
18 GP1 GP2 GP3 GP4
19 fd 17 88 14
20 */
21 const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
22
23 /* Enter super-io's configuration state. */
24 pnp_enter_conf_state(sio);
25
26 /* Set lpc47n227's runtime register block's base address. */
27 pnp_write_config(sio, 0x30, 0x600 >> 4);
28
29 /* Set GP23 to alternate function. */
30 pnp_write_config(sio, 0x33, 0x40);
31
32 /* Set GP30 - GP37 to output mode: COM control */
33 pnp_write_config(sio, 0x35, 0xff);
34
35 /* Set GP45 - GP47 to output mode. */
36 pnp_write_config(sio, 0x37, 0xe0);
37
38 /* Set nIO_PME to open drain. */
39 pnp_write_config(sio, 0x39, 0x80);
40
41 /* Exit configuration state. */
42 pnp_exit_conf_state(sio);
43
44 /* Set GPIO output values: */
45 outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
46 outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
47
48 lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
49 }
50