1chip soc/intel/skylake 2 3 # FSP Configuration 4 register "SkipExtGfxScan" = "1" 5 6 7 # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch 8 register "s0ix_enable" = true 9 register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" 10 register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" 11 register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" 12 register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" 13 14 device domain 0 on 15 device ref sa_thermal on end 16 device ref south_xhci on end 17 device ref thermal on end 18 device ref heci1 on end 19 device ref sata on 20 register "SataSalpSupport" = "1" 21 register "SataPortsEnable" = "{ 22 [0] = 1, 23 [1] = 1, 24 [2] = 1, 25 [3] = 1, 26 [4] = 1, 27 [5] = 1, 28 [6] = 1, 29 [7] = 1, 30 }" 31 end 32 device ref lpc_espi on 33 register "serirq_mode" = "SERIRQ_CONTINUOUS" 34 35 chip superio/common 36 device pnp 2e.0 on end 37 end 38 chip drivers/pc80/tpm # TPM 39 device pnp 0c31.0 on end 40 end 41 end 42 device ref smbus on end 43 device ref fast_spi on end 44 end 45end 46