1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <arch/bootblock.h> 4 #include <assert.h> 5 #include <device/pci_ops.h> 6 #include <types.h> 7 8 #include "i945.h" 9 encode_pciexbar_length(void)10static uint32_t encode_pciexbar_length(void) 11 { 12 switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { 13 case 256: return 0 << 1; 14 case 128: return 1 << 1; 15 case 64: return 2 << 1; 16 default: return dead_code_t(uint32_t); 17 } 18 } 19 bootblock_early_northbridge_init(void)20void bootblock_early_northbridge_init(void) 21 { 22 /* 23 * The "io" variant of the config access is explicitly used to setup the 24 * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way 25 * all subsequent non-explicit config accesses use MCFG. This code also 26 * assumes that bootblock_northbridge_init() is the first thing called 27 * in the non-asm boot block code. The final assumption is that no 28 * assembly code is using the CONFIG(ECAM_MMCONF_SUPPORT) option to do 29 * PCI config accesses. 30 * 31 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. 32 */ 33 const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; 34 pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); 35 } 36