1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/io.h>
4 #include <device/mmio.h>
5 #include <console/console.h>
6 #include <delay.h>
7 #include <device/device.h>
8 #include <device/pci.h>
9 #include <device/pci_ids.h>
10 #include <device/pci_ops.h>
11 #include <drivers/intel/gma/i915_reg.h>
12 #include <drivers/intel/gma/intel_bios.h>
13 #include <drivers/intel/gma/i915.h>
14 #include <drivers/intel/gma/opregion.h>
15 #include <pc80/vga.h>
16 #include <pc80/vga_io.h>
17 #include <types.h>
18
19 #include "chip.h"
20 #include "pineview.h"
21
22 #define GTTSIZE (512 * 1024)
23
24 #define PGETBL2_CTL 0x20c4
25 #define PGETBL2_1MB (1 << 8)
26
27 #define PGETBL_CTL 0x2020
28 #define PGETBL_1MB (3 << 1)
29 #define PGETBL_512KB 0
30 #define PGETBL_ENABLED 0x1
31
32 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
33 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
34 ADPA_CRT_HOTPLUG_MONITOR_COLOR| \
35 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
36 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
37 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
38 ADPA_CRT_HOTPLUG_ENABLE)
39
40 static struct resource *gtt_res = NULL;
41 static struct resource *mmio_res = NULL;
42
gtt_setup(u8 * mmiobase)43 static int gtt_setup(u8 *mmiobase)
44 {
45 u32 gttbase;
46 struct device *dev = pcidev_on_root(0, 0);
47
48 gttbase = pci_read_config32(dev, BGSM);
49 printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
50
51 write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
52 udelay(50);
53 write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
54
55 write32(mmiobase + GFX_FLSH_CNTL, 0);
56
57 return 0;
58 }
59
intel_gma_init(const struct northbridge_intel_pineview_config * info,struct device * vga,u8 * mmio,u8 * gtt,u32 physbase,u16 piobase)60 static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
61 struct device *vga, u8 *mmio, u8 *gtt, u32 physbase, u16 piobase)
62 {
63 int i;
64 u32 hactive, vactive;
65 u32 temp;
66
67 printk(BIOS_SPEW, "gtt %x mmio %x addrport %x physbase %x\n",
68 (u32)gtt, (u32)mmio, piobase, physbase);
69
70 gtt_setup(mmio);
71
72 pci_write_config16(vga, GGC, 0x130);
73
74 /* Disable VGA. */
75 write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
76
77 /* Disable pipes. */
78 write32(mmio + PIPECONF(0), 0);
79 write32(mmio + PIPECONF(1), 0);
80
81 write32(mmio + INSTPM, 0x800);
82
83 vga_gr_write(0x18, 0);
84
85 write32(mmio + VGA0, 0x200074);
86 write32(mmio + VGA1, 0x200074);
87
88 write32(mmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
89 write32(mmio + DSPCLK_GATE_D, 0);
90 write32(mmio + FW_BLC, 0x03060106);
91 write32(mmio + FW_BLC2, 0x00000306);
92
93 write32(mmio + ADPA, ADPA_DAC_ENABLE
94 | ADPA_PIPE_A_SELECT
95 | ADPA_HOTPLUG_BITS
96 | ADPA_USE_VGA_HVPOLARITY
97 | ADPA_VSYNC_CNTL_ENABLE
98 | ADPA_HSYNC_CNTL_ENABLE
99 | ADPA_DPMS_ON);
100
101 write32(mmio + 0x7041c, 0x0);
102
103 write32(mmio + DPLL_MD(0), 0x3);
104 write32(mmio + DPLL_MD(1), 0x3);
105 write32(mmio + DSPCNTR(1), 0x1000000);
106 write32(mmio + PIPESRC(1), 0x027f01df);
107
108 vga_misc_write(0x67);
109 const u8 cr[25] = {
110 0x5f, 0x4f, 0x50, 0x82, 0x55,
111 0x81, 0xbf, 0x1f, 0x00, 0x4f,
112 0x0d, 0x0e, 0x00, 0x00, 0x00,
113 0x00, 0x9c, 0x8e, 0x8f, 0x28,
114 0x1f, 0x96, 0xb9, 0xa3, 0xff,
115 };
116 vga_cr_write(0x11, 0);
117
118 for (i = 0; i < ARRAY_SIZE(cr); i++)
119 vga_cr_write(i, cr[i]);
120
121 // Disable screen memory to prevent garbage from appearing.
122 vga_sr_write(1, vga_sr_read(1) | 0x20);
123 hactive = 640;
124 vactive = 400;
125
126 mdelay(1);
127 write32(mmio + DPLL(0),
128 DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
129 | DPLL_VGA_MODE_DIS
130 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
131 | 0x400601);
132
133 mdelay(1);
134 write32(mmio + DPLL(0),
135 DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
136 | DPLL_VGA_MODE_DIS
137 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
138 | 0x400601);
139
140 write32(mmio + ADPA, ADPA_DAC_ENABLE
141 | ADPA_PIPE_A_SELECT
142 | ADPA_HOTPLUG_BITS
143 | ADPA_USE_VGA_HVPOLARITY
144 | ADPA_VSYNC_CNTL_ENABLE
145 | ADPA_HSYNC_CNTL_ENABLE
146 | ADPA_DPMS_ON);
147
148 write32(mmio + HTOTAL(1), 0x031f027f);
149 write32(mmio + HBLANK(1), 0x03170287);
150 write32(mmio + HSYNC(1), 0x02ef028f);
151 write32(mmio + VTOTAL(1), 0x020c01df);
152 write32(mmio + VBLANK(1), 0x020401e7);
153 write32(mmio + VSYNC(1), 0x01eb01e9);
154
155 write32(mmio + HTOTAL(0), ((hactive - 1) << 16) | (hactive - 1));
156 write32(mmio + HBLANK(0), ((hactive - 1) << 16) | (hactive - 1));
157 write32(mmio + HSYNC(0), ((hactive - 1) << 16) | (hactive - 1));
158 write32(mmio + VTOTAL(0), ((vactive - 1) << 16) | (vactive - 1));
159 write32(mmio + VBLANK(0), ((vactive - 1) << 16) | (vactive - 1));
160 write32(mmio + VSYNC(0), ((vactive - 1) << 16) | (vactive - 1));
161
162 write32(mmio + PF_WIN_POS(0), 0);
163
164 write32(mmio + PIPESRC(0), (639 << 16) | 399);
165 write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
166 write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
167 write32(mmio + PFIT_CONTROL, 0x0);
168
169 mdelay(1);
170
171 write32(mmio + FDI_RX_CTL(0), 0x00002040);
172 mdelay(1);
173 write32(mmio + FDI_RX_CTL(0), 0x80002050);
174 write32(mmio + FDI_TX_CTL(0), 0x00044000);
175 mdelay(1);
176 write32(mmio + FDI_TX_CTL(0), 0x80044000);
177 write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
178
179 write32(mmio + VGACNTRL, 0x0);
180 write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
181 mdelay(1);
182
183 write32(mmio + ADPA, ADPA_DAC_ENABLE
184 | ADPA_PIPE_A_SELECT
185 | ADPA_HOTPLUG_BITS
186 | ADPA_USE_VGA_HVPOLARITY
187 | ADPA_VSYNC_CNTL_ENABLE
188 | ADPA_HSYNC_CNTL_ENABLE
189 | ADPA_DPMS_ON);
190
191 write32(mmio + DSPFW3, 0x7f3f00c1);
192 write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
193 write32(mmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
194 write32(mmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
195
196 for (i = 0; i < (8192 - 512) / 4; i++) {
197 outl((i << 2) | 1, piobase);
198 outl((physbase + (i << 12)) | 1, piobase + 4);
199 }
200
201 temp = read32(mmio + PGETBL_CTL);
202 printk(BIOS_INFO, "GTT PGETBL_CTL register : 0x%08x\n", temp);
203 temp = read32(mmio + PGETBL2_CTL);
204 printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp);
205
206 /* Clear interrupts */
207 write32(mmio + DEIIR, 0xffffffff);
208 write32(mmio + SDEIIR, 0xffffffff);
209 write32(mmio + IIR, 0xffffffff);
210 write32(mmio + IMR, 0xffffffff);
211 write32(mmio + EIR, 0xffffffff);
212
213 vga_textmode_init();
214
215 /* Enable screen memory */
216 vga_sr_write(1, vga_sr_read(1) & ~0x20);
217 }
218
gma_func0_init(struct device * dev)219 static void gma_func0_init(struct device *dev)
220 {
221 intel_gma_init_igd_opregion();
222
223 if (!CONFIG(NO_GFX_INIT))
224 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
225
226 if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
227 /* PCI init, will run VBIOS */
228 pci_dev_init(dev);
229 } else {
230 u32 physbase;
231 struct resource *pio_res;
232 struct northbridge_intel_pineview_config *conf = dev->chip_info;
233
234 int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
235
236 /* Find base addresses */
237 mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
238 gtt_res = find_resource(dev, PCI_BASE_ADDRESS_3);
239 pio_res = find_resource(dev, PCI_BASE_ADDRESS_1);
240 physbase = pci_read_config32(dev, 0x5c) & ~0xf;
241
242 if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
243 if (vga_disable) {
244 printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: "
245 "skipping NATIVE graphic init\n");
246 } else {
247 printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
248 mmio_res->base);
249 intel_gma_init(conf, dev,
250 res2mmio(mmio_res, 0, 0),
251 res2mmio(gtt_res, 0, 0),
252 physbase, pio_res->base);
253 }
254 }
255
256 /* Linux relies on VBT for panel info. */
257 generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW");
258 }
259 }
260
gma_acpi_name(const struct device * dev)261 static const char *gma_acpi_name(const struct device *dev)
262 {
263 return "GFX0";
264 }
265
266 static struct device_operations gma_func0_ops = {
267 .read_resources = pci_dev_read_resources,
268 .set_resources = pci_dev_set_resources,
269 .enable_resources = pci_dev_enable_resources,
270 .init = gma_func0_init,
271 .ops_pci = &pci_dev_ops_pci,
272 .acpi_name = gma_acpi_name,
273 };
274
275 static const unsigned short pci_device_ids[] =
276 {
277 0xa001, 0,
278 };
279
280 static const struct pci_driver gma __pci_driver = {
281 .ops = &gma_func0_ops,
282 .vendor = PCI_VID_INTEL,
283 .devices = pci_device_ids,
284 };
285