1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci_ops.h>
4 #include "sandybridge.h"
5
intel_sandybridge_finalize_smm(void)6 void intel_sandybridge_finalize_smm(void)
7 {
8 pci_or_config16(HOST_BRIDGE, GGC, 1 << 0);
9 pci_or_config16(HOST_BRIDGE, PAVPC, 1 << 2);
10 pci_or_config32(HOST_BRIDGE, DPR, 1 << 0);
11 pci_or_config32(HOST_BRIDGE, MESEG_MASK, MELCK);
12 pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0);
13 pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0);
14 pci_or_config32(HOST_BRIDGE, TOM, 1 << 0);
15 pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0);
16 pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0);
17 pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0);
18 pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0);
19 pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
20
21 mchbar_setbits32(PAVP_MSG, 1 << 0); /* PAVP */
22 mchbar_setbits32(SAPMCTL, 1 << 31); /* SA PM */
23 mchbar_setbits32(UMAGFXCTL, 1 << 0); /* UMA GFX */
24 mchbar_setbits32(VTDTRKLCK, 1 << 0); /* VTDTRK */
25 mchbar_setbits32(REQLIM, 1 << 31);
26 mchbar_setbits32(DMIVCLIM, 1 << 31);
27 mchbar_setbits32(CRDTLCK, 1 << 0);
28
29 /* Memory Controller Lockdown */
30 mchbar_write8(MC_LOCK, 0x8f);
31
32 /* Read+write the following */
33 mchbar_setbits32(VDMBDFBARKVM, 0);
34 mchbar_setbits32(VDMBDFBARPAVP, 0);
35 mchbar_setbits32(HDAUDRID, 0);
36 }
37