1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #include <arch/bootblock.h> 4 #include <assert.h> 5 #include <device/mmio.h> 6 #include <device/pci_ops.h> 7 #include <types.h> 8 9 #include "x4x.h" 10 encode_pciexbar_length(void)11static uint32_t encode_pciexbar_length(void) 12 { 13 switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { 14 case 256: return 0 << 1; 15 case 128: return 1 << 1; 16 case 64: return 2 << 1; 17 default: return dead_code_t(uint32_t); 18 } 19 } 20 bootblock_early_northbridge_init(void)21void bootblock_early_northbridge_init(void) 22 { 23 /* Disable LaGrande Technology (LT) */ 24 read32p(TPM_BASE_ADDRESS); 25 26 const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; 27 pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); 28 } 29