1# SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_CEZANNE 4 bool 5 select ACPI_SOC_NVS 6 select ADD_FSP_BINARIES if USE_AMD_BLOBS 7 select ARCH_X86 8 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH 9 select DRIVERS_USB_ACPI 10 select DRIVERS_USB_PCI_XHCI 11 select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING 12 select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING 13 select FSP_COMPRESS_FSP_S_LZ4 14 select GENERIC_GPIO_LIB 15 select HAVE_ACPI_TABLES 16 select HAVE_CF9_RESET 17 select HAVE_EM100_SUPPORT 18 select HAVE_FSP_GOP 19 select HAVE_SMI_HANDLER 20 select IDT_IN_EVERY_STAGE 21 select PARALLEL_MP_AP_WORK 22 select PLATFORM_USES_FSP2_0 23 select PROVIDES_ROM_SHARING 24 select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK 25 select PSP_VERSTAGE_MAP_ENTIRE_SPIROM if VBOOT_STARTS_BEFORE_BOOTBLOCK 26 select RESET_VECTOR_IN_RAM 27 select RTC 28 select SOC_AMD_COMMON 29 select SOC_AMD_COMMON_BLOCK_ACP_GEN1 30 select SOC_AMD_COMMON_BLOCK_ACPI 31 select SOC_AMD_COMMON_BLOCK_ACPIMMIO 32 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS 33 select SOC_AMD_COMMON_BLOCK_ACPI_ALIB 34 select SOC_AMD_COMMON_BLOCK_ACPI_CPPC 35 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE 36 select SOC_AMD_COMMON_BLOCK_ACPI_GPIO 37 select SOC_AMD_COMMON_BLOCK_ACPI_IVRS 38 select SOC_AMD_COMMON_BLOCK_ACPI_MADT 39 select SOC_AMD_COMMON_BLOCK_AOAC 40 select SOC_AMD_COMMON_BLOCK_APOB 41 select SOC_AMD_COMMON_BLOCK_APOB_HASH 42 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS 43 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H 44 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC 45 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN 46 select SOC_AMD_COMMON_BLOCK_EMMC 47 select SOC_AMD_COMMON_BLOCK_GPP_CLK 48 select SOC_AMD_COMMON_BLOCK_GRAPHICS 49 select SOC_AMD_COMMON_BLOCK_HAS_ESPI 50 select SOC_AMD_COMMON_BLOCK_I2C 51 select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL 52 select SOC_AMD_COMMON_BLOCK_IOMMU 53 select SOC_AMD_COMMON_BLOCK_LPC 54 select SOC_AMD_COMMON_BLOCK_MCAX 55 select SOC_AMD_COMMON_BLOCK_NONCAR 56 select SOC_AMD_COMMON_BLOCK_PCI 57 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF 58 select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER 59 select SOC_AMD_COMMON_BLOCK_PM 60 select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE 61 select SOC_AMD_COMMON_BLOCK_PSP_GEN2 62 select SOC_AMD_COMMON_BLOCK_PSP_SPL 63 select SOC_AMD_COMMON_BLOCK_RESET 64 select SOC_AMD_COMMON_BLOCK_SMBUS 65 select SOC_AMD_COMMON_BLOCK_SMI 66 select SOC_AMD_COMMON_BLOCK_SMM 67 select SOC_AMD_COMMON_BLOCK_SMU 68 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY 69 select SOC_AMD_COMMON_BLOCK_SPI 70 select SOC_AMD_COMMON_BLOCK_SVI2 71 select SOC_AMD_COMMON_BLOCK_TSC 72 select SOC_AMD_COMMON_BLOCK_UART 73 select SOC_AMD_COMMON_BLOCK_UCODE 74 select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB 75 select SOC_AMD_COMMON_FSP_DMI_TABLES 76 select SOC_AMD_COMMON_FSP_PCI 77 select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ 78 select SOC_AMD_COMMON_FSP_PRELOAD_FSPS 79 select SOC_AMD_COMMON_BLOCK_XHCI 80 select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP 81 select SSE2 82 select UDK_2017_BINDING 83 select USE_DDR4 84 select USE_LPDDR4 85 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 86 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 87 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 88 select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK 89 select X86_AMD_FIXED_MTRRS 90 select X86_INIT_NEED_1_SIPI 91 help 92 AMD Cezanne support 93 94if SOC_AMD_CEZANNE 95 96config CHIPSET_DEVICETREE 97 string 98 default "soc/amd/cezanne/chipset.cb" 99 100config FSP_M_FILE 101 string "FSP-M (memory init) binary path and filename" 102 depends on ADD_FSP_BINARIES 103 default "3rdparty/amd_blobs/cezanne/CEZANNE_M.fd" 104 help 105 The path and filename of the FSP-M binary for this platform. 106 107config FSP_S_FILE 108 string "FSP-S (silicon init) binary path and filename" 109 depends on ADD_FSP_BINARIES 110 default "3rdparty/amd_blobs/cezanne/CEZANNE_S.fd" 111 help 112 The path and filename of the FSP-S binary for this platform. 113 114config EARLY_RESERVED_DRAM_BASE 115 hex 116 default 0x2000000 117 help 118 This variable defines the base address of the DRAM which is reserved 119 for usage by coreboot in early stages (i.e. before ramstage is up). 120 This memory gets reserved in BIOS tables to ensure that the OS does 121 not use it, thus preventing corruption of OS memory in case of S3 122 resume. 123 124config EARLYRAM_BSP_STACK_SIZE 125 hex 126 default 0x1000 127 128config PSP_APOB_DRAM_ADDRESS 129 hex 130 default 0x2001000 131 help 132 Location in DRAM where the PSP will copy the AGESA PSP Output 133 Block. 134 135config PSP_APOB_DRAM_SIZE 136 hex 137 default 0x10000 138 139config PSP_SHAREDMEM_BASE 140 hex 141 default 0x2011000 if VBOOT 142 default 0x0 143 help 144 This variable defines the base address in DRAM memory where PSP copies 145 the vboot workbuf. This is used in the linker script to have a static 146 allocation for the buffer as well as for adding relevant entries in 147 the BIOS directory table for the PSP. 148 149config PSP_SHAREDMEM_SIZE 150 hex 151 default 0x8000 if VBOOT 152 default 0x0 153 help 154 Sets the maximum size for the PSP to pass the vboot workbuf and 155 any logs or timestamps back to coreboot. This will be copied 156 into main memory by the PSP and will be available when the x86 is 157 started. The workbuf's base depends on the address of the reset 158 vector. 159 160config PRE_X86_CBMEM_CONSOLE_SIZE 161 hex 162 default 0x1600 163 help 164 Size of the CBMEM console used in PSP verstage. 165 166config PRERAM_CBMEM_CONSOLE_SIZE 167 hex 168 default 0x2000 169 help 170 Increase this value if preram cbmem console is getting truncated 171 172config CBFS_MCACHE_SIZE 173 hex 174 default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK 175 176config C_ENV_BOOTBLOCK_SIZE 177 hex 178 default 0x20000 179 help 180 Sets the size of the bootblock stage that should be loaded in DRAM. 181 This variable controls the DRAM allocation size in linker script 182 for bootblock stage. 183 184config ROMSTAGE_ADDR 185 hex 186 default 0x2050000 187 help 188 Sets the address in DRAM where romstage should be loaded. 189 190config ROMSTAGE_SIZE 191 hex 192 default 0x70000 193 help 194 Sets the size of DRAM allocation for romstage in linker script. 195 196config FSP_M_ADDR 197 hex 198 default 0x20C0000 199 help 200 Sets the address in DRAM where FSP-M should be loaded. cbfstool 201 performs relocation of FSP-M to this address. 202 203config FSP_M_SIZE 204 hex 205 default 0xC0000 206 help 207 Sets the size of DRAM allocation for FSP-M in linker script. 208 209config FSP_TEMP_RAM_SIZE 210 hex 211 default 0x40000 212 help 213 The amount of coreboot-allocated heap and stack usage by the FSP. 214 215config VERSTAGE_ADDR 216 hex 217 depends on VBOOT_SEPARATE_VERSTAGE 218 default 0x2180000 219 help 220 Sets the address in DRAM where verstage should be loaded if running 221 as a separate stage on x86. 222 223config VERSTAGE_SIZE 224 hex 225 depends on VBOOT_SEPARATE_VERSTAGE 226 default 0x80000 227 help 228 Sets the size of DRAM allocation for verstage in linker script if 229 running as a separate stage on x86. 230 231config ASYNC_FILE_LOADING 232 bool "Loads files from SPI asynchronously" 233 select COOP_MULTITASKING 234 select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA 235 select CBFS_PRELOAD 236 help 237 When enabled, the platform will use the LPC SPI DMA controller to 238 asynchronously load contents from the SPI ROM. This will improve 239 boot time because the CPUs can be performing useful work while the 240 SPI contents are being preloaded. 241 242config CBFS_CACHE_SIZE 243 hex 244 default 0x40000 if CBFS_PRELOAD 245 246config RO_REGION_ONLY 247 string 248 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A 249 default "apu/amdfw" 250 251config ECAM_MMCONF_BASE_ADDRESS 252 default 0xF8000000 253 254config ECAM_MMCONF_BUS_NUMBER 255 default 64 256 257config MAX_CPUS 258 int 259 default 16 260 help 261 Maximum number of threads the platform can have. 262 263config VGA_BIOS_ID 264 string 265 default "1002,1638" 266 help 267 The default VGA BIOS PCI vendor/device ID should be set to the 268 result of the map_oprom_vendev() function in grapthics.c. 269 270config VGA_BIOS_FILE 271 string 272 default "3rdparty/amd_blobs/cezanne/CezanneGenericVbios.bin" 273 274config CONSOLE_UART_BASE_ADDRESS 275 depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART 276 hex 277 default 0xfedc9000 if UART_FOR_CONSOLE = 0 278 default 0xfedca000 if UART_FOR_CONSOLE = 1 279 280config SMM_TSEG_SIZE 281 hex 282 default 0x800000 if HAVE_SMI_HANDLER 283 default 0x0 284 285config SMM_RESERVED_SIZE 286 hex 287 default 0x180000 288 289config SMM_MODULE_STACK_SIZE 290 hex 291 default 0x800 292 293config ACPI_BERT 294 bool "Build ACPI BERT Table" 295 default y 296 depends on HAVE_ACPI_TABLES 297 help 298 Report Machine Check errors identified in POST to the OS in an 299 ACPI Boot Error Record Table. 300 301config ACPI_BERT_SIZE 302 hex 303 default 0x4000 if ACPI_BERT 304 default 0x0 305 help 306 Specify the amount of DRAM reserved for gathering the data used to 307 generate the ACPI table. 308 309config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 310 int 311 default 150 312 313config DISABLE_SPI_FLASH_ROM_SHARING 314 def_bool n 315 help 316 Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin 317 which indicates a board level ROM transaction request. This 318 removes arbitration with board and assumes the chipset controls 319 the SPI flash bus entirely. 320 321config DISABLE_KEYBOARD_RESET_PIN 322 bool 323 help 324 Instruct the SoC to not use the state of GPIO_129 as keyboard reset 325 signal. When this pin is used as GPIO and the keyboard reset 326 functionality isn't disabled, configuring it as an output and driving 327 it as 0 will cause a reset. 328 329menu "PSP Configuration Options" 330 331config AMDFW_CONFIG_FILE 332 string 333 default "src/soc/amd/cezanne/fw.cfg" 334 335config PSP_DISABLE_POSTCODES 336 bool "Disable PSP post codes" 337 help 338 Disables the output of port80 post codes from PSP. 339 340config PSP_POSTCODES_ON_ESPI 341 bool "Use eSPI bus for PSP post codes" 342 depends on !PSP_DISABLE_POSTCODES 343 default y 344 help 345 Select to send PSP port80 post codes on eSPI bus. 346 If not selected, PSP port80 codes will be sent on LPC bus. 347 348config PSP_INIT_ESPI 349 bool "Initialize eSPI in PSP Stage 2 Boot Loader" 350 help 351 Select to initialize the eSPI controller in the PSP Stage 2 Boot 352 Loader. 353 354config PSP_LOAD_MP2_FW 355 bool 356 default n 357 help 358 Include the MP2 firmwares and configuration into the PSP build. 359 360 If unsure, answer 'n' 361 362config PSP_UNLOCK_SECURE_DEBUG 363 bool "Unlock secure debug" 364 default y 365 help 366 Select this item to enable secure debug options in PSP. 367 368config HAVE_PSP_WHITELIST_FILE 369 bool "Include a debug whitelist file in PSP build" 370 default n 371 help 372 Support secured unlock prior to reset using a whitelisted 373 serial number. This feature requires a signed whitelist image 374 and bootloader from AMD. 375 376 If unsure, answer 'n' 377 378config PSP_WHITELIST_FILE 379 string "Debug whitelist file path" 380 depends on HAVE_PSP_WHITELIST_FILE 381 default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" 382 383config PSP_SOFTFUSE_BITS 384 string "PSP Soft Fuse bits to enable" 385 default "28 6" 386 help 387 Space separated list of Soft Fuse bits to enable. 388 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) 389 Bit 7: Disable PSP postcodes on Renoir and newer chips only 390 (Set by PSP_DISABLE_PORT80) 391 Bit 15: PSP post code destination: 0=LPC 1=eSPI 392 (Set by PSP_INITIALIZE_ESPI) 393 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) 394 395 See #55758 (NDA) for additional bit definitions. 396 397config PSP_VERSTAGE_FILE 398 string "Specify the PSP_verstage file path" 399 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 400 default "\$(obj)/psp_verstage.bin" 401 help 402 Add psp_verstage file to the build & PSP Directory Table 403 404config PSP_VERSTAGE_SIGNING_TOKEN 405 string "Specify the PSP_verstage Signature Token file path" 406 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 407 default "" 408 help 409 Add psp_verstage signature token to the build & PSP Directory Table 410 411endmenu 412 413config VBOOT 414 select VBOOT_VBNV_CMOS 415 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 416 417config VBOOT_STARTS_BEFORE_BOOTBLOCK 418 def_bool n 419 depends on VBOOT 420 select ARCH_VERSTAGE_ARMV7 421 help 422 Runs verstage on the PSP. Only available on 423 certain ChromeOS branded parts from AMD. 424 425config VBOOT_HASH_BLOCK_SIZE 426 hex 427 default 0x9000 428 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 429 help 430 Because the bulk of the time in psp_verstage to hash the RO cbfs is 431 spent in the overhead of doing svc calls, increasing the hash block 432 size significantly cuts the verstage hashing time as seen below. 433 434 4k takes 180ms 435 16k takes 44ms 436 32k takes 33.7ms 437 36k takes 32.5ms 438 There's actually still room for an even bigger stack, but we've 439 reached a point of diminishing returns. 440 441config CMOS_RECOVERY_BYTE 442 hex 443 default 0x51 444 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 445 help 446 If the workbuf is not passed from the PSP to coreboot, set the 447 recovery flag and reboot. The PSP will read this byte, mark the 448 recovery request in VBNV, and reset the system into recovery mode. 449 450 This is the byte before the default first byte used by VBNV 451 (0x26 + 0x0E - 1) 452 453if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK 454 455config RWA_REGION_ONLY 456 string 457 default "apu/amdfw_a" 458 help 459 Add a space-delimited list of filenames that should only be in the 460 RW-A section. 461 462endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK 463 464if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 465 466config RWB_REGION_ONLY 467 string 468 default "apu/amdfw_b" 469 help 470 Add a space-delimited list of filenames that should only be in the 471 RW-B section. 472 473endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 474 475endif # SOC_AMD_CEZANNE 476