1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <amdblocks/acpimmio.h> 4 #include <amdblocks/lpc.h> 5 #include <device/pci_ops.h> 6 #include <soc/espi.h> 7 #include <soc/lpc.h> 8 #include <soc/pci_devs.h> 9 #include <soc/southbridge.h> 10 #include <types.h> 11 espi_disable_lpc_ldrq(void)12void espi_disable_lpc_ldrq(void) 13 { 14 /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped 15 on Picasso and older compared to Renoir/Cezanne and newer */ 16 uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); 17 dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); 18 dword |= LPC_LDRQ0_PD_EN; 19 pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); 20 } 21 espi_switch_to_spi2_pads(void)22void espi_switch_to_spi2_pads(void) 23 { 24 /* Use SPI2 pins for eSPI */ 25 uint32_t dword = pm_read32(PM_SPI_PAD_PU_PD); 26 dword |= PM_ESPI_CS_USE_DATA2; 27 pm_write32(PM_SPI_PAD_PU_PD, dword); 28 29 /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ 30 dword = pm_read32(PM_ACPI_CONF); 31 dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; 32 pm_write32(PM_ACPI_CONF, dword); 33 } 34