1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpigen.h>
4 #include <amdblocks/alib.h>
5 #include <amdblocks/data_fabric.h>
6 #include <amdblocks/ioapic.h>
7 #include <amdblocks/root_complex.h>
8 #include <arch/ioapic.h>
9 #include <device/device.h>
10 #include <device/pci.h>
11 #include <soc/iomap.h>
12 #include <stdint.h>
13 #include "chip.h"
14
15 #define DPTC_TOTAL_UPDATE_PARAMS 4
16
17 struct dptc_input {
18 uint16_t size;
19 struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS];
20 } __packed;
21
22 #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \
23 { \
24 .size = sizeof(struct dptc_input), \
25 .params = { \
26 { \
27 .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \
28 .value = _thermctllmit, \
29 }, \
30 { \
31 .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \
32 .value = _sustained, \
33 }, \
34 { \
35 .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \
36 .value = _fast, \
37 }, \
38 { \
39 .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \
40 .value = _slow, \
41 }, \
42 }, \
43 }
44
acipgen_dptci(void)45 static void acipgen_dptci(void)
46 {
47 const struct soc_amd_cezanne_config *config = config_of_soc();
48
49 /* Normal mode DPTC values. */
50 struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
51 config->sustained_power_limit_mW,
52 config->fast_ppt_limit_mW,
53 config->slow_ppt_limit_mW);
54 acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
55 }
56
root_complex_fill_ssdt(const struct device * device)57 static void root_complex_fill_ssdt(const struct device *device)
58 {
59 if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
60 acipgen_dptci();
61 }
62
gnb_acpi_name(const struct device * dev)63 static const char *gnb_acpi_name(const struct device *dev)
64 {
65 return "GNB";
66 }
67
68 struct device_operations cezanne_root_complex_operations = {
69 /* The root complex has no PCI BARs implemented, so there's no need to call
70 pci_dev_read_resources for it */
71 .read_resources = noop_read_resources,
72 .set_resources = noop_set_resources,
73 .enable_resources = pci_dev_enable_resources,
74 .acpi_name = gnb_acpi_name,
75 .acpi_fill_ssdt = root_complex_fill_ssdt,
76 };
77
get_iohc_misc_smn_base(struct device * domain)78 uint32_t get_iohc_misc_smn_base(struct device *domain)
79 {
80 return SMN_IOHC_MISC_BASE_13B1;
81 }
82
83 static const struct non_pci_mmio_reg non_pci_mmio[] = {
84 { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
85 { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
86 { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
87 /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
88 tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
89 resource. */
90 { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX },
91 { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
92 { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
93 { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO },
94 { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
95 };
96
get_iohc_non_pci_mmio_regs(size_t * count)97 const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
98 {
99 *count = ARRAY_SIZE(non_pci_mmio);
100 return non_pci_mmio;
101 }
102
get_iohc_fabric_id(struct device * domain)103 signed int get_iohc_fabric_id(struct device *domain)
104 {
105 switch (domain->path.domain.domain) {
106 case 0:
107 return IOMS0_FABRIC_ID;
108 default:
109 return -1;
110 }
111 }
112