1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_GENOA_POC 4 bool 5 6if SOC_AMD_GENOA_POC 7 8config SOC_SPECIFIC_OPTIONS 9 def_bool y 10 select ACPI_SOC_NVS 11 select ARCH_X86 12 select DEFAULT_X2APIC 13 select HAVE_ACPI_TABLES 14 select HAVE_X86_64_SUPPORT 15 select HAVE_SMI_HANDLER 16 select RESET_VECTOR_IN_RAM 17 select SOC_AMD_COMMON 18 select SOC_AMD_COMMON_BLOCK_ACPI 19 select SOC_AMD_COMMON_BLOCK_ACPIMMIO 20 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE 21 select SOC_AMD_COMMON_BLOCK_ACPI_IVRS 22 select SOC_AMD_COMMON_BLOCK_ACPI_MADT 23 select SOC_AMD_COMMON_BLOCK_AOAC 24 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS 25 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H 26 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC 27 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN 28 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT 29 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO 30 select SOC_AMD_COMMON_BLOCK_HAS_ESPI 31 select SOC_AMD_COMMON_BLOCK_I2C 32 select SOC_AMD_COMMON_BLOCK_IOMMU 33 select SOC_AMD_COMMON_BLOCK_LPC 34 select SOC_AMD_COMMON_BLOCK_MCAX 35 select SOC_AMD_COMMON_BLOCK_NONCAR 36 select SOC_AMD_COMMON_BLOCK_PCI 37 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF 38 select SOC_AMD_COMMON_BLOCK_PSP_GEN2 39 select SOC_AMD_COMMON_BLOCK_PSP_SPL 40 select SOC_AMD_COMMON_BLOCK_SMI 41 select SOC_AMD_COMMON_BLOCK_SMM 42 select SOC_AMD_COMMON_BLOCK_SMU 43 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY 44 select SOC_AMD_COMMON_BLOCK_SVI3 45 select SOC_AMD_COMMON_BLOCK_TSC 46 select SOC_AMD_COMMON_BLOCK_UART 47 select SOC_AMD_COMMON_BLOCK_UCODE 48 select SOC_AMD_COMMON_BLOCK_USE_ESPI 49 select SOC_AMD_OPENSIL 50 select SOC_AMD_OPENSIL_GENOA_POC 51 select X86_CUSTOM_BOOTMEDIA 52 53config USE_X86_64_SUPPORT 54 default y 55 56config CHIPSET_DEVICETREE 57 string 58 default "soc/amd/genoa_poc/chipset.cb" 59 60config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 61 int 62 default 150 63 64config EARLY_RESERVED_DRAM_BASE 65 hex 66 default 0x7000000 67 help 68 This variable defines the base address of the DRAM which is reserved 69 for usage by coreboot in early stages (i.e. before ramstage is up). 70 This memory gets reserved in BIOS tables to ensure that the OS does 71 not use it, thus preventing corruption of OS memory in case of S3 72 resume. 73 74config EARLYRAM_BSP_STACK_SIZE 75 hex 76 default 0x1000 77 78config MAX_CPUS 79 int 80 default 384 81 82config PSP_APOB_DRAM_ADDRESS 83 hex 84 default 0x7001000 85 help 86 Location in DRAM where the PSP will copy the AGESA PSP Output 87 Block. 88 89config PSP_APOB_DRAM_SIZE 90 hex 91 default 0x20000 92 93config PRERAM_CBMEM_CONSOLE_SIZE 94 hex 95 default 0x1600 96 help 97 Increase this value if preram cbmem console is getting truncated 98 99config C_ENV_BOOTBLOCK_SIZE 100 hex 101 default 0x20000 102 help 103 Sets the size of the bootblock stage that should be loaded in DRAM. 104 This variable controls the DRAM allocation size in linker script 105 for bootblock stage. 106 107config ROMSTAGE_ADDR 108 hex 109 default 0x7050000 110 help 111 Sets the address in DRAM where romstage should be loaded. 112 113config ROMSTAGE_SIZE 114 hex 115 default 0x70000 116 help 117 Sets the size of DRAM allocation for romstage in linker script. 118 119config ECAM_MMCONF_BASE_ADDRESS 120 hex 121 default 0xE0000000 122 123config ECAM_MMCONF_BUS_NUMBER 124 int 125 default 256 126 127menu "PSP Configuration Options" 128 129config AMDFW_CONFIG_FILE 130 string 131 default "src/soc/amd/genoa_poc/fw.cfg" 132 133config PSP_DISABLE_POSTCODES 134 bool "Disable PSP post codes" 135 help 136 Disables the output of port80 post codes from PSP. 137 138config PSP_INIT_ESPI 139 bool "Initialize eSPI in PSP Stage 2 Boot Loader" 140 help 141 Select to initialize the eSPI controller in the PSP Stage 2 Boot 142 Loader. 143 144config PSP_UNLOCK_SECURE_DEBUG 145 bool 146 default y 147 148config HAVE_PSP_WHITELIST_FILE 149 bool "Include a debug whitelist file in PSP build" 150 default n 151 help 152 Support secured unlock prior to reset using a whitelisted 153 serial number. This feature requires a signed whitelist image 154 and bootloader from AMD. 155 156 If unsure, answer 'n' 157 158config PSP_WHITELIST_FILE 159 string "Debug whitelist file path" 160 depends on HAVE_PSP_WHITELIST_FILE 161 162config PSP_SOFTFUSE_BITS 163 string "PSP Soft Fuse bits to enable" 164 default "" 165 help 166 Space separated list of Soft Fuse bits to enable. 167 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) 168 Bit 7: Disable PSP postcodes on Renoir and newer chips only 169 (Set by PSP_DISABLE_PORT80) 170 Bit 15: PSP debug output destination: 171 0=SoC MMIO UART, 1=IO port 0x3F8 172 173 See #57299 (NDA) for additional bit definitions. 174endmenu 175 176config CONSOLE_UART_BASE_ADDRESS 177 depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART 178 hex 179 default 0xfedc9000 if UART_FOR_CONSOLE = 0 180 default 0xfedca000 if UART_FOR_CONSOLE = 1 181 default 0xfedce000 if UART_FOR_CONSOLE = 2 182 183config SMM_TSEG_SIZE 184 hex 185 default 0x800000 186 187config ACPI_SSDT_PSD_INDEPENDENT 188 bool "Allow core p-state independent transitions" 189 default y 190 help 191 AMD recommends the ACPI _PSD object to be configured to cause 192 cores to transition between p-states independently. A vendor may 193 choose to generate _PSD object to allow cores to transition together. 194 195config ACPI_BERT 196 bool "Build ACPI BERT Table" 197 default y 198 depends on HAVE_ACPI_TABLES 199 help 200 Report Machine Check errors identified in POST to the OS in an 201 ACPI Boot Error Record Table. 202 203config ACPI_BERT_SIZE 204 hex 205 default 0x4000 if ACPI_BERT 206 default 0x0 207 help 208 Specify the amount of DRAM reserved for gathering the data used to 209 generate the ACPI table. 210 211endif # SOC_AMD_GENOA_POC 212