1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <amdblocks/i2c.h>
4 #include <soc/i2c.h>
5 #include <soc/southbridge.h>
6 #include "chip.h"
7
8 /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
9 static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
10 I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
11 I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
12 I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
13 I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
14 I2C_RESET_SCL_PIN(I2C4_SCL_PIN, GPIO_I2C4_SCL),
15 I2C_RESET_SCL_PIN(I2C5_SCL_PIN, GPIO_I2C5_SCL),
16 };
17
18 static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
19 { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
20 { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" },
21 { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
22 { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" },
23 { I2C_MASTER_MODE, APU_I2C4_BASE, "I2C4" },
24 { I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" }
25 };
26
reset_i2c_peripherals(void)27 void reset_i2c_peripherals(void)
28 {
29 const struct soc_amd_genoa_poc_config *cfg = config_of_soc();
30 struct soc_i2c_peripheral_reset_info reset_info;
31
32 reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
33 reset_info.i2c_scl = i2c_scl_pins;
34 reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
35 sb_reset_i2c_peripherals(&reset_info);
36 }
37
soc_i2c_misc_init(unsigned int bus,const struct dw_i2c_bus_config * cfg)38 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
39 {
40 /* TODO: write I2C pad control registers */
41 }
42
soc_get_i2c_ctrlr_info(size_t * num_ctrlrs)43 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
44 {
45 *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
46 return i2c_ctrlr;
47 }
48
soc_get_i2c_bus_config(size_t * num_buses)49 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
50 {
51 const struct soc_amd_genoa_poc_config *config = config_of_soc();
52
53 *num_buses = ARRAY_SIZE(config->i2c);
54 return config->i2c;
55 }
56