1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <amdblocks/mca.h>
4 #include <cpu/x86/msr.h>
5 #include <types.h>
6
7 /* TODO: Check if non-core MCA banks are same for all cores */
8 static const char *const mca_bank_name[] = {
9 [0] = "Load-store unit",
10 [1] = "Instruction fetch unit",
11 [2] = "L2 cache unit",
12 [3] = "Decode unit",
13 [4] = "",
14 [5] = "Execution unit",
15 [6] = "Floating point unit",
16 [7] = "L3 cache unit",
17 [8] = "L3 cache unit",
18 [9] = "L3 cache unit",
19 [10] = "L3 cache unit",
20 [11] = "L3 cache unit",
21 [12] = "L3 cache unit",
22 [13] = "L3 cache unit",
23 [14] = "L3 cache unit",
24 [15] = "Microprocessor5 Management Controller",
25 [16] = "Parameter Block",
26 [17] = "GMI Controller",
27 [18] = "GMI Controller",
28 [19] = "High Speed Interface Unit (GMI)",
29 [20] = "High Speed Interface Unit (GMI)",
30 [21] = "Unified Memory Controller",
31 [22] = "Unified Memory Controller",
32 [23] = "Coherent Station",
33 [24] = "Coherent Station",
34 [25] = "Northbridge IO Unit",
35 [26] = "PCIe Root Port",
36 [27] = "PCIe Root Port",
37 [28] = "Power Management, Interrupts, Etc.",
38 [29] = "SMU",
39 [30] = "XGMI Controller",
40 [31] = "High Speed Interface Unit (XGMI)",
41 };
42
mca_has_expected_bank_count(void)43 bool mca_has_expected_bank_count(void)
44 {
45 return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count();
46 }
47
mca_is_valid_bank(unsigned int bank)48 bool mca_is_valid_bank(unsigned int bank)
49 {
50 return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL);
51 }
52
mca_get_bank_name(unsigned int bank)53 const char *mca_get_bank_name(unsigned int bank)
54 {
55 if (mca_is_valid_bank(bank))
56 return mca_bank_name[bank];
57 else
58 return "";
59 }
60