1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /* TODO: Update for Glinda */
4
5 #include <amdblocks/i2c.h>
6 #include <console/console.h>
7 #include <soc/i2c.h>
8 #include <soc/southbridge.h>
9 #include "chip.h"
10
11 /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
12 static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
13 I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
14 I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
15 I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
16 I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
17 };
18
19 #if ENV_X86
20 static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
21 { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
22 { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" },
23 { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
24 { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" }
25 };
26 #else
27 static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
28 { I2C_MASTER_MODE, 0, "" },
29 { I2C_MASTER_MODE, 0, "" },
30 { I2C_MASTER_MODE, 0, "" },
31 { I2C_MASTER_MODE, 0, "" }
32 };
33
i2c_set_bar(unsigned int bus,uintptr_t bar)34 void i2c_set_bar(unsigned int bus, uintptr_t bar)
35 {
36 if (bus >= ARRAY_SIZE(i2c_ctrlr)) {
37 printk(BIOS_ERR, "i2c index out of bounds: %u.", bus);
38 return;
39 }
40
41 i2c_ctrlr[bus].bar = bar;
42 }
43 #endif
44
reset_i2c_peripherals(void)45 void reset_i2c_peripherals(void)
46 {
47 const struct soc_amd_glinda_config *cfg = config_of_soc();
48 struct soc_i2c_peripheral_reset_info reset_info;
49
50 reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
51 reset_info.i2c_scl = i2c_scl_pins;
52 reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
53 sb_reset_i2c_peripherals(&reset_info);
54 }
55
soc_i2c_misc_init(unsigned int bus,const struct dw_i2c_bus_config * cfg)56 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
57 {
58 const struct soc_amd_glinda_config *config = config_of_soc();
59
60 if (bus >= ARRAY_SIZE(config->i2c_pad))
61 return;
62
63 fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
64 }
65
soc_get_i2c_ctrlr_info(size_t * num_ctrlrs)66 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
67 {
68 *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
69 return i2c_ctrlr;
70 }
71
soc_get_i2c_bus_config(size_t * num_buses)72 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
73 {
74 const struct soc_amd_glinda_config *config = config_of_soc();
75
76 *num_buses = ARRAY_SIZE(config->i2c);
77 return config->i2c;
78 }
79