1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef MENDOCINO_CHIP_H 4 #define MENDOCINO_CHIP_H 5 6 #include <amdblocks/chip.h> 7 #include <amdblocks/i2c.h> 8 #include <amdblocks/pci_clk_req.h> 9 #include <gpio.h> 10 #include <soc/i2c.h> 11 #include <soc/southbridge.h> 12 #include <drivers/i2c/designware/dw_i2c.h> 13 #include <types.h> 14 #include <vendorcode/amd/fsp/mendocino/FspUsb.h> 15 16 /* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */ 17 union __packed usb3_force_gen1 { 18 struct { 19 uint8_t xhci0_port0:1; 20 uint8_t xhci1_port0:1; 21 uint8_t xhci1_port1:1; 22 } ports; 23 uint8_t usb3_port_force_gen1_en; 24 }; 25 26 struct soc_amd_mendocino_config { 27 struct soc_amd_common_config common_config; 28 u8 i2c_scl_reset; 29 struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; 30 struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; 31 32 /* Enable S0iX support */ 33 bool s0ix_enable; 34 35 enum { 36 DOWNCORE_AUTO = 0, 37 DOWNCORE_1 = 1, /* Run with 1 physical core */ 38 DOWNCORE_2 = 3, /* Run with 2 physical cores */ 39 DOWNCORE_3 = 4, /* Run with 3 physical cores */ 40 DOWNCORE_4 = 6, /* Run with 4 physical cores */ 41 DOWNCORE_5 = 8, /* Run with 5 physical cores */ 42 DOWNCORE_6 = 9, /* Run with 6 physical cores */ 43 DOWNCORE_7 = 10, /* Run with 7 physical cores */ 44 } downcore_mode; 45 bool disable_smt; /* disable second thread on all physical cores */ 46 47 uint8_t stt_control; 48 uint8_t stt_pcb_sensor_count; 49 uint16_t stt_min_limit; 50 uint16_t stt_m1; 51 uint16_t stt_m2; 52 uint16_t stt_m3; 53 uint16_t stt_m4; 54 uint16_t stt_m5; 55 uint16_t stt_m6; 56 uint16_t stt_c_apu; 57 uint16_t stt_c_gpu; 58 uint16_t stt_c_hs2; 59 uint16_t stt_alpha_apu; 60 uint16_t stt_alpha_gpu; 61 uint16_t stt_alpha_hs2; 62 uint16_t stt_skin_temp_apu; 63 uint16_t stt_skin_temp_gpu; 64 uint16_t stt_skin_temp_hs2; 65 uint16_t stt_error_coeff; 66 uint16_t stt_error_rate_coefficient; 67 68 /* Default */ 69 uint8_t stapm_boost; 70 uint32_t stapm_time_constant_s; 71 uint32_t apu_only_sppt_limit; 72 uint32_t sustained_power_limit_mW; 73 uint32_t fast_ppt_limit_mW; 74 uint32_t slow_ppt_limit_mW; 75 uint32_t slow_ppt_time_constant_s; 76 uint32_t thermctl_limit_degreeC; 77 uint32_t vrm_current_limit_mA; 78 uint32_t vrm_maximum_current_limit_mA; 79 uint32_t vrm_soc_current_limit_mA; 80 /* Throttle (e.g., Low/No Battery) */ 81 uint32_t vrm_current_limit_throttle_mA; 82 uint32_t vrm_maximum_current_limit_throttle_mA; 83 uint32_t vrm_soc_current_limit_throttle_mA; 84 85 /* tablet mode.*/ 86 uint16_t stt_m1_tablet; 87 uint16_t stt_m2_tablet; 88 uint16_t stt_c_apu_tablet; 89 uint16_t stt_alpha_apu_tablet; 90 91 /* Thermal profile B*/ 92 uint32_t fast_ppt_limit_mW_B; 93 uint32_t slow_ppt_limit_mW_B; 94 uint32_t slow_ppt_time_constant_s_B; 95 uint16_t stt_min_limit_B; 96 uint16_t stt_m1_B; 97 uint16_t stt_m2_B; 98 uint16_t stt_c_apu_B; 99 uint16_t stt_skin_temp_apu_B; 100 101 /* Thermal profile C*/ 102 uint32_t fast_ppt_limit_mW_C; 103 uint32_t slow_ppt_limit_mW_C; 104 uint32_t slow_ppt_time_constant_s_C; 105 uint16_t stt_min_limit_C; 106 uint16_t stt_m1_C; 107 uint16_t stt_m2_C; 108 uint16_t stt_c_apu_C; 109 uint16_t stt_skin_temp_apu_C; 110 111 /* Thermal profile D*/ 112 uint32_t fast_ppt_limit_mW_D; 113 uint32_t slow_ppt_limit_mW_D; 114 uint32_t slow_ppt_time_constant_s_D; 115 uint16_t stt_min_limit_D; 116 uint16_t stt_m1_D; 117 uint16_t stt_m2_D; 118 uint16_t stt_c_apu_D; 119 uint16_t stt_skin_temp_apu_D; 120 121 /* Thermal profile E*/ 122 uint32_t fast_ppt_limit_mW_E; 123 uint32_t slow_ppt_limit_mW_E; 124 uint32_t slow_ppt_time_constant_s_E; 125 uint16_t stt_min_limit_E; 126 uint16_t stt_m1_E; 127 uint16_t stt_m2_E; 128 uint16_t stt_c_apu_E; 129 uint16_t stt_skin_temp_apu_E; 130 131 132 /* Thermal profile F*/ 133 uint32_t fast_ppt_limit_mW_F; 134 uint32_t slow_ppt_limit_mW_F; 135 uint32_t slow_ppt_time_constant_s_F; 136 uint16_t stt_min_limit_F; 137 uint16_t stt_m1_F; 138 uint16_t stt_m2_F; 139 uint16_t stt_c_apu_F; 140 uint16_t stt_skin_temp_apu_F; 141 142 uint8_t smartshift_enable; 143 144 uint8_t system_configuration; 145 146 uint8_t cppc_ctrl; 147 uint8_t cppc_perf_limit_max_range; 148 uint8_t cppc_perf_limit_min_range; 149 uint8_t cppc_epp_max_range; 150 uint8_t cppc_epp_min_range; 151 uint8_t cppc_preferred_cores; 152 153 /* telemetry settings */ 154 uint32_t telemetry_vddcrvddfull_scale_current_mA; 155 uint32_t telemetry_vddcrvddoffset; 156 uint32_t telemetry_vddcrsocfull_scale_current_mA; 157 uint32_t telemetry_vddcrsocoffset; 158 159 /* The array index is the general purpose PCIe clock output number. Values in here 160 aren't the values written to the register to have the default to be always on. */ 161 enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; 162 163 /* performance policy for the PCIe links: power consumption vs. link speed */ 164 enum { 165 DXIO_PSPP_DISABLED = 0, 166 DXIO_PSPP_PERFORMANCE, 167 DXIO_PSPP_BALANCED, 168 DXIO_PSPP_POWERSAVE, 169 } pspp_policy; 170 171 uint8_t usb_phy_custom; 172 struct usb_phy_config usb_phy; 173 /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal 174 Integrity is highly recommended. */ 175 uint8_t dxio_tx_vboost_enable; 176 177 /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ 178 union usb3_force_gen1 usb3_port_force_gen1; 179 180 /* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */ 181 uint8_t edp_panel_t8_ms; 182 /* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */ 183 uint8_t edp_panel_t9_ms; 184 185 }; 186 187 #endif /* MENDOCINO_CHIP_H */ 188