1# SPDX-License-Identifier: GPL-2.0-only 2 3# TODO: Evaluate what can be moved to a common directory 4# TODO: Update for Phoenix 5 6config SOC_AMD_PHOENIX_BASE 7 bool 8 select ACPI_SOC_NVS 9 select ARCH_X86 10 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH 11 select CACHE_MRC_SETTINGS 12 select DRIVERS_USB_ACPI 13 select DRIVERS_USB_PCI_XHCI 14 select GENERIC_GPIO_LIB 15 select HAVE_ACPI_TABLES 16 select HAVE_CF9_RESET 17 select HAVE_EM100_SUPPORT 18 select HAVE_SMI_HANDLER 19 select IDT_IN_EVERY_STAGE 20 select PARALLEL_MP_AP_WORK 21 select PROVIDES_ROM_SHARING 22 select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK 23 # TODO: (b/303516266) Re-enable CCP DMA after addressing a stall 24 # select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK 25 select RESET_VECTOR_IN_RAM 26 select RTC 27 select SOC_AMD_COMMON 28 select SOC_AMD_COMMON_BLOCK_ACP_GEN2 29 select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct 30 select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct 31 select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct 32 select SOC_AMD_COMMON_BLOCK_ACPI_CPPC if !SOC_AMD_PHOENIX_OPENSIL # TODO: add support for openSIL case 33 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE 34 select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct 35 select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct 36 select SOC_AMD_COMMON_BLOCK_ACPI_MADT 37 select SOC_AMD_COMMON_BLOCK_AOAC 38 select SOC_AMD_COMMON_BLOCK_APOB 39 select SOC_AMD_COMMON_BLOCK_APOB_HASH 40 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS 41 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H 42 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC 43 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN 44 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT 45 select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES 46 select SOC_AMD_COMMON_BLOCK_GPP_CLK 47 select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct 48 select SOC_AMD_COMMON_BLOCK_HAS_ESPI 49 select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE 50 select SOC_AMD_COMMON_BLOCK_I2C 51 select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL 52 select SOC_AMD_COMMON_BLOCK_IOMMU 53 select SOC_AMD_COMMON_BLOCK_LPC 54 select SOC_AMD_COMMON_BLOCK_MCAX 55 select SOC_AMD_COMMON_BLOCK_NONCAR 56 select SOC_AMD_COMMON_BLOCK_PCI 57 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF 58 select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER 59 select SOC_AMD_COMMON_BLOCK_PM 60 select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE 61 select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct 62 select SOC_AMD_COMMON_BLOCK_PSP_SPL 63 select SOC_AMD_COMMON_BLOCK_RESET 64 select SOC_AMD_COMMON_BLOCK_SMBUS 65 select SOC_AMD_COMMON_BLOCK_SMI 66 select SOC_AMD_COMMON_BLOCK_SMM 67 select SOC_AMD_COMMON_BLOCK_SMU 68 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY 69 select SOC_AMD_COMMON_BLOCK_SPI 70 select SOC_AMD_COMMON_BLOCK_SVI3 71 select SOC_AMD_COMMON_BLOCK_TSC 72 select SOC_AMD_COMMON_BLOCK_UART 73 select SOC_AMD_COMMON_BLOCK_UCODE 74 select SOC_AMD_COMMON_BLOCK_XHCI 75 select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP 76 select SSE2 77 select USE_DDR5 78 select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK 79 select VBOOT_X86_SHA256_ACCELERATION if VBOOT 80 select X86_AMD_FIXED_MTRRS 81 select X86_INIT_NEED_1_SIPI 82 83config SOC_AMD_PHOENIX_FSP 84 bool 85 select SOC_AMD_PHOENIX_BASE 86 select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING 87 select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING 88 select FSP_COMPRESS_FSP_S_LZ4 89 select HAVE_FSP_GOP 90 select PLATFORM_USES_FSP2_0 91 select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB 92 select SOC_AMD_COMMON_FSP_DMI_TABLES 93 select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct 94 select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ 95 select SOC_AMD_COMMON_FSP_PRELOAD_FSPS 96 select UDK_2017_BINDING 97 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 98 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 99 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 100 help 101 AMD Phoenix support using FSP 102 103config SOC_AMD_PHOENIX_OPENSIL 104 bool 105 select SOC_AMD_PHOENIX_BASE 106 select SOC_AMD_OPENSIL 107 108if SOC_AMD_PHOENIX_BASE 109 110config CHIPSET_DEVICETREE 111 string 112 default "soc/amd/phoenix/chipset_fsp.cb" if SOC_AMD_PHOENIX_FSP 113 default "soc/amd/phoenix/chipset_opensil.cb" 114 115config EARLY_RESERVED_DRAM_BASE 116 hex 117 default 0x2000000 118 help 119 This variable defines the base address of the DRAM which is reserved 120 for usage by coreboot in early stages (i.e. before ramstage is up). 121 This memory gets reserved in BIOS tables to ensure that the OS does 122 not use it, thus preventing corruption of OS memory in case of S3 123 resume. 124 125config EARLYRAM_BSP_STACK_SIZE 126 hex 127 default 0x1000 128 129config PSP_APOB_DRAM_ADDRESS 130 hex 131 default 0x2001000 132 help 133 Location in DRAM where the PSP will copy the AGESA PSP Output 134 Block. 135 136config PSP_APOB_DRAM_SIZE 137 hex 138 default 0x40000 139 140config PSP_SHAREDMEM_BASE 141 hex 142 default 0x2041000 if VBOOT 143 default 0x0 144 help 145 This variable defines the base address in DRAM memory where PSP copies 146 the vboot workbuf. This is used in the linker script to have a static 147 allocation for the buffer as well as for adding relevant entries in 148 the BIOS directory table for the PSP. 149 150config PSP_SHAREDMEM_SIZE 151 hex 152 default 0x8000 if VBOOT 153 default 0x0 154 help 155 Sets the maximum size for the PSP to pass the vboot workbuf and 156 any logs or timestamps back to coreboot. This will be copied 157 into main memory by the PSP and will be available when the x86 is 158 started. The workbuf's base depends on the address of the reset 159 vector. 160 161config PRE_X86_CBMEM_CONSOLE_SIZE 162 hex 163 default 0x1600 164 help 165 Size of the CBMEM console used in PSP verstage. 166 167config PRERAM_CBMEM_CONSOLE_SIZE 168 hex 169 default 0x1600 170 help 171 Increase this value if preram cbmem console is getting truncated 172 173config CBFS_MCACHE_SIZE 174 hex 175 default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK 176 177config C_ENV_BOOTBLOCK_SIZE 178 hex 179 default 0x20000 180 help 181 Sets the size of the bootblock stage that should be loaded in DRAM. 182 This variable controls the DRAM allocation size in linker script 183 for bootblock stage. 184 185config ROMSTAGE_ADDR 186 hex 187 default 0x2070000 188 help 189 Sets the address in DRAM where romstage should be loaded. 190 191config ROMSTAGE_SIZE 192 hex 193 default 0x70000 194 help 195 Sets the size of DRAM allocation for romstage in linker script. 196 197config VERSTAGE_ADDR 198 hex 199 depends on VBOOT_SEPARATE_VERSTAGE 200 default 0x21A0000 201 help 202 Sets the address in DRAM where verstage should be loaded if running 203 as a separate stage on x86. 204 205config VERSTAGE_SIZE 206 hex 207 depends on VBOOT_SEPARATE_VERSTAGE 208 default 0x80000 209 help 210 Sets the size of DRAM allocation for verstage in linker script if 211 running as a separate stage on x86. 212 213config ASYNC_FILE_LOADING 214 bool "Loads files from SPI asynchronously" 215 select COOP_MULTITASKING 216 select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA 217 select CBFS_PRELOAD 218 help 219 When enabled, the platform will use the LPC SPI DMA controller to 220 asynchronously load contents from the SPI ROM. This will improve 221 boot time because the CPUs can be performing useful work while the 222 SPI contents are being preloaded. 223 224config CBFS_CACHE_SIZE 225 hex 226 default 0x40000 if CBFS_PRELOAD 227 228config RO_REGION_ONLY 229 string 230 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A 231 default "apu/amdfw" 232 233config ECAM_MMCONF_BASE_ADDRESS 234 default 0xE0000000 235 236config ECAM_MMCONF_BUS_NUMBER 237 default 256 238 239config MAX_CPUS 240 int 241 default 16 242 help 243 Maximum number of threads the platform can have. 244 245config VGA_BIOS_ID 246 string 247 default "1002,15bf" 248 help 249 The default VGA BIOS PCI vendor/device ID should be set to the 250 result of the map_oprom_vendev() function in graphics.c. 251 252# TODO: add VGA_BIOS_FILE default once the correct VBIOS binaries are available in amd_blobs 253 254config CONSOLE_UART_BASE_ADDRESS 255 depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART 256 hex 257 default 0xfedc9000 if UART_FOR_CONSOLE = 0 258 default 0xfedca000 if UART_FOR_CONSOLE = 1 259 default 0xfedce000 if UART_FOR_CONSOLE = 2 260 default 0xfedcf000 if UART_FOR_CONSOLE = 3 261 default 0xfedd1000 if UART_FOR_CONSOLE = 4 262 263config SMM_TSEG_SIZE 264 hex 265 default 0x800000 if HAVE_SMI_HANDLER 266 default 0x0 267 268config SMM_RESERVED_SIZE 269 hex 270 default 0x180000 271 272config SMM_MODULE_STACK_SIZE 273 hex 274 default 0x800 275 276config ACPI_BERT 277 bool "Build ACPI BERT Table" 278 default y 279 depends on HAVE_ACPI_TABLES 280 help 281 Report Machine Check errors identified in POST to the OS in an 282 ACPI Boot Error Record Table. 283 284config ACPI_BERT_SIZE 285 hex 286 default 0x4000 if ACPI_BERT 287 default 0x0 288 help 289 Specify the amount of DRAM reserved for gathering the data used to 290 generate the ACPI table. 291 292config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 293 int 294 default 150 295 296config DISABLE_SPI_FLASH_ROM_SHARING 297 def_bool n 298 help 299 Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin 300 which indicates a board level ROM transaction request. This 301 removes arbitration with board and assumes the chipset controls 302 the SPI flash bus entirely. 303 304config DISABLE_KEYBOARD_RESET_PIN 305 bool 306 help 307 Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L. 308 309menu "PSP Configuration Options" 310 311config AMDFW_CONFIG_FILE 312 string "AMD PSP Firmware config file" 313 default "src/soc/amd/phoenix/fw.cfg" 314 help 315 Specify the path/location of AMD PSP Firmware config file. 316 317config PSP_DISABLE_POSTCODES 318 bool "Disable PSP post codes" 319 help 320 Disables the output of port80 post codes from PSP. 321 322config PSP_POSTCODES_ON_ESPI 323 bool "Use eSPI bus for PSP post codes" 324 default y 325 depends on !PSP_DISABLE_POSTCODES 326 help 327 Select to send PSP port80 post codes on eSPI bus. 328 If not selected, PSP port80 codes will be sent on LPC bus. 329 330config PSP_LOAD_MP2_FW 331 bool 332 default n 333 help 334 Include the MP2 firmwares and configuration into the PSP build. 335 336 If unsure, answer 'n' 337 338config PSP_UNLOCK_SECURE_DEBUG 339 bool "Unlock secure debug" 340 default y 341 help 342 Select this item to enable secure debug options in PSP. 343 344config HAVE_PSP_WHITELIST_FILE 345 bool "Include a debug whitelist file in PSP build" 346 default n 347 help 348 Support secured unlock prior to reset using a whitelisted 349 serial number. This feature requires a signed whitelist image 350 and bootloader from AMD. 351 352 If unsure, answer 'n' 353 354config PSP_WHITELIST_FILE 355 string "Debug whitelist file path" 356 depends on HAVE_PSP_WHITELIST_FILE 357 default "site-local/3rdparty/amd_blobs/phoenix/PSP/wtl-phx.sbin" 358 359config PSP_SOFTFUSE_BITS 360 string "PSP Soft Fuse bits to enable" 361 default "36 28 6" 362 help 363 Space separated list of Soft Fuse bits to enable. 364 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) 365 Bit 7: Disable PSP postcodes on Renoir and newer chips only 366 (Set by PSP_DISABLE_PORT80) 367 Bit 15: PSP debug output destination: 368 0=SoC MMIO UART, 1=IO port 0x3F8 369 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) 370 371 See #55758 (NDA) for additional bit definitions. 372 373config PSP_VERSTAGE_FILE 374 string "Specify the PSP_verstage file path" 375 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 376 default "\$(obj)/psp_verstage.bin" 377 help 378 Add psp_verstage file to the build & PSP Directory Table 379 380config PSP_VERSTAGE_SIGNING_TOKEN 381 string "Specify the PSP_verstage Signature Token file path" 382 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 383 default "" 384 help 385 Add psp_verstage signature token to the build & PSP Directory Table 386 387endmenu 388 389config VBOOT 390 select VBOOT_VBNV_CMOS 391 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 392 393config VBOOT_STARTS_BEFORE_BOOTBLOCK 394 def_bool n 395 depends on VBOOT 396 select ARCH_VERSTAGE_ARMV7 397 help 398 Runs verstage on the PSP. Only available on 399 certain ChromeOS branded parts from AMD. 400 401config VBOOT_HASH_BLOCK_SIZE 402 hex 403 default 0x9000 404 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 405 help 406 Because the bulk of the time in psp_verstage to hash the RO cbfs is 407 spent in the overhead of doing svc calls, increasing the hash block 408 size significantly cuts the verstage hashing time as seen below. 409 410 4k takes 180ms 411 16k takes 44ms 412 32k takes 33.7ms 413 36k takes 32.5ms 414 There's actually still room for an even bigger stack, but we've 415 reached a point of diminishing returns. 416 417config CMOS_RECOVERY_BYTE 418 hex 419 default 0x51 420 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 421 help 422 If the workbuf is not passed from the PSP to coreboot, set the 423 recovery flag and reboot. The PSP will read this byte, mark the 424 recovery request in VBNV, and reset the system into recovery mode. 425 426 This is the byte before the default first byte used by VBNV 427 (0x26 + 0x0E - 1) 428 429if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 430 431config RWA_REGION_ONLY 432 string 433 default "apu/amdfw_a" 434 help 435 Add a space-delimited list of filenames that should only be in the 436 RW-A section. 437 438config RWB_REGION_ONLY 439 string 440 default "apu/amdfw_b" 441 help 442 Add a space-delimited list of filenames that should only be in the 443 RW-B section. 444 445endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 446 447endif # SOC_AMD_PHOENIX_BASE 448 449if SOC_AMD_PHOENIX_FSP 450 451config FSP_M_ADDR 452 hex 453 default 0x20E0000 454 help 455 Sets the address in DRAM where FSP-M should be loaded. cbfstool 456 performs relocation of FSP-M to this address. 457 458config FSP_M_SIZE 459 hex 460 default 0xC0000 461 help 462 Sets the size of DRAM allocation for FSP-M in linker script. 463 464config FSP_TEMP_RAM_SIZE 465 hex 466 default 0x40000 467 help 468 The amount of coreboot-allocated heap and stack usage by the FSP. 469 470endif # SOC_AMD_PHOENIX_FSP 471 472if SOC_AMD_PHOENIX_OPENSIL 473 474config SOC_AMD_OPENSIL_STUB 475 prompt "Build with openSIL stub" 476 default y 477 478endif # SOC_AMD_PHOENIX_OPENSIL 479