1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <bootstate.h>
5 #include <cpu/x86/smm.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pci_ops.h>
9 #include <amdblocks/amd_pci_util.h>
10 #include <amdblocks/pci_clk_req.h>
11 #include <amdblocks/reset.h>
12 #include <amdblocks/acpimmio.h>
13 #include <amdblocks/acpi.h>
14 #include <amdblocks/gpio.h>
15 #include <amdblocks/i2c.h>
16 #include <amdblocks/smi.h>
17 #include <soc/cpu.h>
18 #include <soc/i2c.h>
19 #include <soc/iomap.h>
20 #include <soc/southbridge.h>
21 #include <soc/smi.h>
22 #include <soc/amd_pci_int_defs.h>
23 #include <soc/pci_devs.h>
24 #include <types.h>
25 #include "chip.h"
26
27 /*
28 * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
29 * provides a visible association with the index, therefore helping
30 * maintainability of table. If a new index/name is defined in
31 * amd_pci_int_defs.h, just add the pair at the end of this table.
32 * Order is not important.
33 */
34 static const struct irq_idx_name irq_association[] = {
35 { PIRQ_A, "INTA#" },
36 { PIRQ_B, "INTB#" },
37 { PIRQ_C, "INTC#" },
38 { PIRQ_D, "INTD#" },
39 { PIRQ_E, "INTE#" },
40 { PIRQ_F, "INTF#/GENINT2" },
41 { PIRQ_G, "INTG#" },
42 { PIRQ_H, "INTH#" },
43 { PIRQ_MISC, "Misc" },
44 { PIRQ_MISC0, "Misc0" },
45 { PIRQ_MISC1, "Misc1" },
46 { PIRQ_MISC2, "Misc2" },
47 { PIRQ_SIRQA, "Ser IRQ INTA" },
48 { PIRQ_SIRQB, "Ser IRQ INTB" },
49 { PIRQ_SIRQC, "Ser IRQ INTC" },
50 { PIRQ_SIRQD, "Ser IRQ INTD" },
51 { PIRQ_SCI, "SCI" },
52 { PIRQ_SMBUS, "SMBUS" },
53 { PIRQ_ASF, "ASF" },
54 { PIRQ_PMON, "PerMon" },
55 { PIRQ_SD, "SD" },
56 { PIRQ_SDIO, "SDIO" },
57 { PIRQ_CIR, "CIR" },
58 { PIRQ_GPIOA, "GPIOa" },
59 { PIRQ_GPIOB, "GPIOb" },
60 { PIRQ_GPIOC, "GPIOc" },
61 { PIRQ_SATA, "SATA" },
62 { PIRQ_EMMC, "eMMC" },
63 { PIRQ_GPP0, "GPP0" },
64 { PIRQ_GPP1, "GPP1" },
65 { PIRQ_GPP2, "GPP2" },
66 { PIRQ_GPP3, "GPP3" },
67 { PIRQ_GPIO, "GPIO" },
68 { PIRQ_I2C0, "I2C0" },
69 { PIRQ_I2C1, "I2C1" },
70 { PIRQ_I2C2, "I2C2" },
71 { PIRQ_I2C3, "I2C3" },
72 { PIRQ_UART0, "UART0" },
73 { PIRQ_UART1, "UART1" },
74 { PIRQ_I2C4, "I2C4" },
75 { PIRQ_I2C5, "I2C5" },
76 { PIRQ_UART2, "UART2" },
77 { PIRQ_UART3, "UART3" },
78 };
79
sb_get_apic_reg_association(size_t * size)80 const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
81 {
82 *size = ARRAY_SIZE(irq_association);
83 return irq_association;
84 }
85
fch_clk_output_48Mhz(void)86 static void fch_clk_output_48Mhz(void)
87 {
88 u32 ctrl;
89 const struct soc_amd_picasso_config *cfg = config_of_soc();
90
91 ctrl = misc_read32(MISC_CLK_CNTL1);
92 /* If used external clock source for I2S, disable the internal clock output */
93 if (cfg->acp_i2s_use_external_48mhz_osc &&
94 cfg->common_config.acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM)
95 ctrl &= ~BP_X48M0_OUTPUT_EN;
96 else
97 ctrl |= BP_X48M0_OUTPUT_EN;
98 misc_write32(MISC_CLK_CNTL1, ctrl);
99 }
100
sb_rfmux_config_override(void)101 static void sb_rfmux_config_override(void)
102 {
103 u8 port;
104 const struct soc_amd_picasso_config *cfg;
105
106 cfg = config_of_soc();
107
108 for (port = 0; port < USB_PD_PORT_COUNT; port++) {
109 if (cfg->usb_pd_config_override[port].rfmux_override_en) {
110 write32p(USB_PD_PORT_CONTROL + PD_PORT_MUX_OFFSET(port),
111 cfg->usb_pd_config_override[port].rfmux_config
112 | USB_PD_RFMUX_OVERRIDE);
113 }
114 }
115 }
116
fch_init_acpi_ports(void)117 static void fch_init_acpi_ports(void)
118 {
119 u32 reg;
120
121 /* We use some of these ports in SMM regardless of whether or not
122 * ACPI tables are generated. Enable these ports indiscriminately.
123 */
124
125 pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
126 pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
127 pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
128 pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
129
130 if (CONFIG(HAVE_SMI_HANDLER)) {
131 /* APMC - SMI Command Port */
132 pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
133 configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
134
135 /* SMI on SlpTyp requires sending SMI before completion
136 response of the I/O write. */
137 reg = pm_read32(PM_PCI_CTRL);
138 reg |= FORCE_SLPSTATE_RETRY;
139 pm_write32(PM_PCI_CTRL, reg);
140
141 /* Disable SlpTyp feature */
142 reg = pm_read8(PM_RST_CTRL1);
143 reg &= ~SLPTYPE_CONTROL_EN;
144 pm_write8(PM_RST_CTRL1, reg);
145
146 configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
147 } else {
148 pm_write16(PM_ACPI_SMI_CMD, 0);
149 }
150
151 /* Decode ACPI registers and enable standard features */
152 pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
153 PM_ACPI_GLOBAL_EN |
154 PM_ACPI_RTC_EN_EN |
155 PM_ACPI_TIMER_EN_EN);
156 }
157
158 /*
159 * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks
160 * and unneeded for Raven/Picasso so gate them to save power.
161 */
al2ahb_clock_gate(void)162 static void al2ahb_clock_gate(void)
163 {
164 uint8_t al2ahb_val;
165 uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
166
167 al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET);
168 al2ahb_val |= AL2AHB_CLK_GATE_EN;
169 write8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET, al2ahb_val);
170 al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET);
171 al2ahb_val |= AL2AHB_HCLK_GATE_EN;
172 write8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET, al2ahb_val);
173 }
174
175 /* configure the general purpose PCIe clock outputs according to the devicetree settings */
gpp_clk_setup(void)176 static void gpp_clk_setup(void)
177 {
178 struct soc_amd_picasso_config *cfg = config_of_soc();
179 gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
180 }
181
fch_init(void * chip_info)182 void fch_init(void *chip_info)
183 {
184 i2c_soc_init();
185 fch_init_acpi_ports();
186
187 acpi_pm_gpe_add_events_print_events();
188 gpio_add_events();
189
190 al2ahb_clock_gate();
191
192 gpp_clk_setup();
193
194 fch_clk_output_48Mhz();
195
196 sb_rfmux_config_override();
197 }
198
fch_final(void * chip_info)199 void fch_final(void *chip_info)
200 {
201 }
202
203 /*
204 * Update the PCI devices with a valid IRQ number
205 * that is set in the mainboard PCI_IRQ structures.
206 */
set_pci_irqs(void * unused)207 static void set_pci_irqs(void *unused)
208 {
209 /* Write PCI_INTR regs 0xC00/0xC01 */
210 write_pci_int_table();
211
212 /* pirq_data is consumed by `write_pci_cfg_irqs` */
213 populate_pirq_data();
214
215 /* Write IRQs for all devicetree enabled devices */
216 write_pci_cfg_irqs();
217 }
218
219 /*
220 * Hook this function into the PCI state machine
221 * on entry into BS_DEV_ENABLE.
222 */
223 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
224