1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
5 */
6
7 #include <console/console.h>
8 #include <soc/sdram.h>
9
10 #include <libbdk-arch/bdk-warn.h>
11 #include <libbdk-arch/bdk-csrs-rst.h>
12 #include <libbdk-boot/bdk-watchdog.h>
13 #include <libbdk-dram/bdk-dram-config.h>
14 #include <libbdk-dram/bdk-dram-test.h>
15 #include <libbdk-hal/bdk-config.h>
16 #include <libbdk-hal/bdk-utils.h>
17 #include <libbdk-hal/bdk-l2c.h>
18 #include <libdram/libdram-config.h>
19 #include <soc/ecam.h>
20 #include <device/pci_ops.h>
21 #include <device/mmio.h>
22 #include <device/pci.h>
23
sdram_size_mb(void)24 size_t sdram_size_mb(void)
25 {
26 return bdk_dram_get_size_mbytes(0);
27 }
28
29 #define BDK_RNM_CTL_STATUS 0
30 #define BDK_RNM_RANDOM 0x100000
31
32 #if ENV_RAMINIT
33 /* Enable RNG for DRAM init */
rnm_init(void)34 static void rnm_init(void)
35 {
36 /* Bus numbers are hardcoded in ASIC. No need to program bridges. */
37 pci_devfn_t dev = PCI_DEV(2, 0, 0);
38
39 u64 *bar = (u64 *)ecam0_get_bar_val(dev, 0);
40 if (!bar) {
41 printk(BIOS_ERR, "RNG: Failed to get BAR0\n");
42 return;
43 }
44
45 printk(BIOS_DEBUG, "RNG: BAR0 at %p\n", bar);
46
47 u64 reg = read64(&bar[BDK_RNM_CTL_STATUS]);
48 /*
49 * Enables the output of the RNG.
50 * Entropy enable for random number generator.
51 */
52 reg |= 3;
53 write64(&bar[BDK_RNM_CTL_STATUS], reg);
54
55 /* Read back after enable so we know it is done. */
56 reg = read64(&bar[BDK_RNM_CTL_STATUS]);
57 /*
58 * Errata (RNM-22528) First consecutive reads to RNM_RANDOM return same
59 * value. Before using the random entropy, read RNM_RANDOM at least once
60 * and discard the data
61 */
62 reg = read64(&bar[BDK_RNM_RANDOM]);
63 printk(BIOS_SPEW, "RNG: RANDOM %llx\n", reg);
64 reg = read64(&bar[BDK_RNM_RANDOM]);
65 printk(BIOS_SPEW, "RNG: RANDOM %llx\n", reg);
66 }
67
68 /* based on bdk_boot_dram() */
sdram_init(void)69 void sdram_init(void)
70 {
71 printk(BIOS_DEBUG, "Initializing DRAM\n");
72
73 rnm_init();
74
75 /**
76 * FIXME: second arg is actually a desired frequency if set (the
77 * function usually obtains frequency via the config). That might
78 * be useful if FDT or u-boot env is too cumbersome.
79 */
80 int mbytes = bdk_dram_config(0, 0);
81 if (mbytes < 0) {
82 bdk_error("N0: Failed DRAM init\n");
83 die("DRAM INIT FAILED !\n");
84 }
85
86 /* Poke the watchdog */
87 bdk_watchdog_poke();
88
89 /* Report DRAM status */
90 printf("N0: DRAM:%s\n", bdk_dram_get_info_string(0));
91
92 /* See if we should test this node's DRAM during boot */
93 int test_dram = bdk_config_get_int(BDK_CONFIG_DRAM_BOOT_TEST, 0);
94 if (test_dram == 1) {
95 static const u8 tests[] = {13, 0, 1};
96 for (size_t i = 0; i < ARRAY_SIZE(tests); i++) {
97 /* Run the address test to make sure DRAM works */
98 if (bdk_dram_test(tests[i], 4 * MiB,
99 sdram_size_mb() * MiB - 4 * MiB,
100 BDK_DRAM_TEST_NO_STATS |
101 BDK_DRAM_TEST_NODE0)) {
102 printk(BIOS_CRIT, "%s: Failed DRAM test.\n",
103 __func__);
104 }
105 bdk_watchdog_poke();
106 }
107 } else {
108 /* Run the address test to make sure DRAM works */
109 if (bdk_dram_test(13, 4 * MiB,
110 sdram_size_mb() * MiB - 4 * MiB,
111 BDK_DRAM_TEST_NO_STATS |
112 BDK_DRAM_TEST_NODE0)) {
113 /**
114 * FIXME(dhendrix): This should be handled by mainboard
115 * code since we don't necessarily have a BMC to report
116 * to. Also, we need to figure out if we need to keep
117 * going as to avoid getting into a boot loop.
118 */
119 // bdk_boot_status(BDK_BOOT_STATUS_REQUEST_POWER_CYCLE);
120 printk(BIOS_CRIT, "%s: Failed DRAM test.\n", __func__);
121 }
122 }
123
124 bdk_watchdog_poke();
125
126 /* Unlock L2 now that DRAM works */
127 if (0 == bdk_numa_master()) {
128 uint64_t l2_size = bdk_l2c_get_cache_size_bytes(0);
129 BDK_TRACE(INIT, "Unlocking L2\n");
130 bdk_l2c_unlock_mem_region(0, 0, l2_size);
131 bdk_watchdog_poke();
132 }
133
134 printk(BIOS_INFO, "SDRAM initialization finished.\n");
135 }
136 #endif
137