1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * This file is created based on Intel Alder Lake Processor PCH Datasheet
5 * Document number: 621483
6 * Chapter number: 4, 29
7 */
8
9 #include <bootstate.h>
10 #include <commonlib/console/post_codes.h>
11 #include <console/console.h>
12 #include <cpu/x86/smm.h>
13 #include <device/mmio.h>
14 #include <device/pci.h>
15 #include <intelblocks/cse.h>
16 #include <intelblocks/lpc_lib.h>
17 #include <intelblocks/pcr.h>
18 #include <intelblocks/pmclib.h>
19 #include <intelblocks/systemagent.h>
20 #include <intelblocks/tco.h>
21 #include <soc/p2sb.h>
22 #include <soc/pci_devs.h>
23 #include <soc/pcr_ids.h>
24 #include <soc/pm.h>
25 #include <soc/smbus.h>
26 #include <soc/soc_chip.h>
27 #include <soc/systemagent.h>
28 #include <spi-generic.h>
29
30 #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
31 #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
32 #define CAM_CLK_EN (1 << 1)
33 #define MIPI_CLK (1 << 0)
34 #define HDPLL_CLK (0 << 0)
35
pch_enable_isclk(void)36 static void pch_enable_isclk(void)
37 {
38 pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
39 pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
40 }
41
pch_handle_sideband(config_t * config)42 static void pch_handle_sideband(config_t *config)
43 {
44 if (config->pch_isclk)
45 pch_enable_isclk();
46 }
47
pch_finalize(void)48 static void pch_finalize(void)
49 {
50 config_t *config = config_of_soc();
51
52 /* TCO Lock down */
53 tco_lockdown();
54
55 /* TODO: Add Thermal Configuration */
56
57 pch_handle_sideband(config);
58
59 pmc_clear_pmcon_sts();
60 }
61
tbt_finalize(void)62 static void tbt_finalize(void)
63 {
64 int i;
65 const struct device *dev;
66
67 /* Disable Thunderbolt PCIe root ports bus master */
68 for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
69 dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
70 if (dev)
71 pci_dev_disable_bus_master(dev);
72 }
73 }
74
heci_finalize(void)75 static void heci_finalize(void)
76 {
77 heci_set_to_d0i3();
78 if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
79 heci1_disable();
80 }
81
soc_finalize(void * unused)82 static void soc_finalize(void *unused)
83 {
84 printk(BIOS_DEBUG, "Finalizing chipset.\n");
85
86 pch_finalize();
87 apm_control(APM_CNT_FINALIZE);
88 tbt_finalize();
89 if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
90 CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
91 heci_finalize();
92
93 /* Indicate finalize step with post code */
94 post_code(POSTCODE_OS_BOOT);
95 }
96
97 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
98 /*
99 * The purpose of this change is to accommodate more time to push out sending
100 * CSE EOP messages at post.
101 */
102 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);
103