1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_BAYTRAIL 4 bool 5 select ACPI_COMMON_MADT_IOAPIC 6 select ACPI_COMMON_MADT_LAPIC 7 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 8 select ARCH_X86 9 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES 10 select BOOT_DEVICE_SUPPORTS_WRITES 11 select CACHE_MRC_SETTINGS 12 select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED 13 select SUPPORT_CPU_UCODE_IN_CBFS 14 select HAVE_SMI_HANDLER 15 select SOUTHBRIDGE_INTEL_COMMON_RESET 16 select SOUTHBRIDGE_INTEL_COMMON_SMBUS 17 select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT 18 select PCIEXP_ASPM 19 select PCIEXP_COMMON_CLOCK 20 select REG_SCRIPT 21 select RTC 22 select SPI_FLASH 23 select SSE2 24 select TSC_MONOTONIC_TIMER 25 select TSC_SYNC_MFENCE 26 select UDELAY_TSC 27 select SOC_INTEL_COMMON 28 select INTEL_DESCRIPTOR_MODE_CAPABLE 29 select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT 30 select INTEL_GMA_ACPI 31 select INTEL_GMA_SWSMISCI 32 select CPU_INTEL_COMMON 33 select CPU_HAS_L2_ENABLE_MSR 34 select TCO_SPACE_NOT_YET_SPLIT 35 select USE_DDR3 36 select NEED_SMALL_2MB_PAGE_TABLES 37 help 38 Bay Trail M/D part support. 39 40if SOC_INTEL_BAYTRAIL 41 42config VBOOT 43 select VBOOT_MUST_REQUEST_DISPLAY 44 select VBOOT_STARTS_IN_ROMSTAGE 45 46config ECAM_MMCONF_BASE_ADDRESS 47 default 0xe0000000 48 49config ECAM_MMCONF_BUS_NUMBER 50 int 51 default 256 52 53config MAX_CPUS 54 int 55 default 4 56 57config SMM_TSEG_SIZE 58 hex 59 default 0x800000 60 61config SMM_RESERVED_SIZE 62 hex 63 default 0x100000 64 65config HAVE_MRC 66 bool "Add a System Agent binary" 67 help 68 Select this option to add a System Agent binary to 69 the resulting coreboot image. 70 71 Note: Without this binary coreboot will not work 72 73config MRC_FILE 74 string "Intel System Agent path and filename" 75 depends on HAVE_MRC 76 default "mrc.bin" 77 help 78 The path and filename of the file to use as System Agent 79 binary. 80 81config MRC_BIN_ADDRESS 82 hex 83 default 0xfffa0000 84 85config MRC_RMT 86 bool "Enable MRC RMT training + debug prints" 87 default n 88 89# Cache As RAM region layout: 90# 91# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE 92# | MRC usage | 93# | | 94# -------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE 95# | coreboot | 96# | usage | 97# +-------------+ DCACHE_RAM_BASE 98# 99# Note that the MRC binary is linked to assume the region marked as "MRC usage" 100# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then 101# a new MRC binary needs to be produced with the updated start and size 102# information. 103 104config DCACHE_RAM_BASE 105 hex 106 default 0xfe000000 107 108config DCACHE_RAM_SIZE 109 hex 110 default 0x8000 111 help 112 The size of the cache-as-ram region required during bootblock 113 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE 114 must add up to a power of 2. 115 116config PRERAM_CBFS_CACHE_SIZE 117 default 0x0 118 119config DCACHE_RAM_MRC_VAR_SIZE 120 hex 121 default 0x8000 122 help 123 The amount of cache-as-ram region required by the reference code. 124 125config DCACHE_BSP_STACK_SIZE 126 hex 127 default 0x2000 128 129config ENABLE_BUILTIN_COM1 130 bool "Enable builtin COM1 Serial Port" 131 default n 132 help 133 The PMC has a legacy COM1 serial port. Choose this option to 134 configure the pads and enable it. This serial port can be used for 135 the debug console. 136 137config HAVE_REFCODE_BLOB 138 depends on ARCH_X86 139 bool "Use a binary refcode blob instead of native ModPHY init" 140 default n 141 help 142 Use the ChromeBook refcode to initialize high-speed PHYs instead of 143 native code. 144 145if HAVE_REFCODE_BLOB 146 147# Ask for the blob if the user wants it 148config REFCODE_BLOB_FILE 149 string "Path and filename to reference code blob." 150 default "refcode.elf" 151 help 152 The path and filename to the file to be added to cbfs. 153 154endif # HAVE_REFCODE_BLOB 155 156config VGA_BIOS_ID 157 string 158 depends on VGA_BIOS 159 default "8086,0f31" 160 161endif 162