1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpi.h>
4 #include <acpi/acpigen.h>
5 #include <arch/ioapic.h>
6 #include <device/mmio.h>
7 #include <arch/smp/mpspec.h>
8 #include <console/console.h>
9 #include <types.h>
10 #include <cpu/x86/msr.h>
11 #include <cpu/intel/turbo.h>
12
13 #include <soc/iomap.h>
14 #include <soc/irq.h>
15 #include <soc/msr.h>
16 #include <soc/pattrs.h>
17 #include <soc/pm.h>
18
19 #define MWAIT_RES(state, sub_state) \
20 { \
21 .addrl = (((state) << 4) | (sub_state)), \
22 .space_id = ACPI_ADDRESS_SPACE_FIXED, \
23 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
24 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
25 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
26 }
27
28 /* C-state map without S0ix */
29 static const acpi_cstate_t cstate_map[] = {
30 {
31 /* C1 */
32 .ctype = 1, /* ACPI C1 */
33 .latency = 1,
34 .power = 1000,
35 .resource = MWAIT_RES(0, 0),
36 },
37 {
38 /* C6NS with no L2 shrink */
39 /* NOTE: this substate is above CPUID limit */
40 .ctype = 2, /* ACPI C2 */
41 .latency = 500,
42 .power = 10,
43 .resource = MWAIT_RES(5, 1),
44 },
45 {
46 /* C6FS with full L2 shrink */
47 .ctype = 3, /* ACPI C3 */
48 .latency = 1500, /* 1.5ms worst case */
49 .power = 1,
50 .resource = MWAIT_RES(5, 2),
51 }
52 };
53
soc_madt_sci_irq_polarity(u8 sci_irq)54 static u8 soc_madt_sci_irq_polarity(u8 sci_irq)
55 {
56 if (sci_irq >= 20)
57 return MP_IRQ_POLARITY_LOW;
58 else
59 return MP_IRQ_POLARITY_HIGH;
60 }
61
62 #define ACPI_SCI_IRQ 9
63
ioapic_get_sci_pin(u8 * gsi,u8 * irq,u8 * flags)64 void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
65 {
66 u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
67 int sci_irq = ACPI_SCI_IRQ;
68 int scis;
69
70 /* Determine how SCI is routed. */
71 scis = read32(actl) & SCIS_MASK;
72 switch (scis) {
73 case SCIS_IRQ9:
74 case SCIS_IRQ10:
75 case SCIS_IRQ11:
76 sci_irq = scis - SCIS_IRQ9 + 9;
77 break;
78 case SCIS_IRQ20:
79 case SCIS_IRQ21:
80 case SCIS_IRQ22:
81 case SCIS_IRQ23:
82 sci_irq = scis - SCIS_IRQ20 + 20;
83 break;
84 default:
85 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq);
86 break;
87 }
88
89 *gsi = sci_irq;
90 *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ;
91 *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq);
92
93 printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi);
94 }
95
96 static acpi_tstate_t soc_tss_table[] = {
97 { 100, 1000, 0, 0x00, 0 },
98 { 88, 875, 0, 0x1e, 0 },
99 { 75, 750, 0, 0x1c, 0 },
100 { 63, 625, 0, 0x1a, 0 },
101 { 50, 500, 0, 0x18, 0 },
102 { 38, 375, 0, 0x16, 0 },
103 { 25, 250, 0, 0x14, 0 },
104 { 13, 125, 0, 0x12, 0 },
105 };
106
generate_t_state_entries(int core,int cores_per_package)107 static void generate_t_state_entries(int core, int cores_per_package)
108 {
109 /* Indicate SW_ALL coordination for T-states */
110 acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
111
112 /* Indicate FFixedHW so OS will use MSR */
113 acpigen_write_empty_PTC();
114
115 /* Set NVS controlled T-state limit */
116 acpigen_write_TPC("\\TLVL");
117
118 /* Write TSS table for MSR access */
119 acpigen_write_TSS_package(ARRAY_SIZE(soc_tss_table), soc_tss_table);
120 }
121
calculate_power(int tdp,int p1_ratio,int ratio)122 static int calculate_power(int tdp, int p1_ratio, int ratio)
123 {
124 u32 m, power;
125
126 /*
127 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
128 */
129
130 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
131 m = (m * m) / 1000;
132
133 /*
134 * Power = (ratio / p1_ratio) * m * TDP
135 */
136 power = ((ratio * 100000 / p1_ratio) / 100);
137 power *= (m / 100) * (tdp / 1000);
138 power /= 1000;
139
140 return (int)power;
141 }
142
generate_p_state_entries(int core)143 static void generate_p_state_entries(int core)
144 {
145 int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
146 int coord_type, power_max, power_unit, num_entries;
147 int ratio, power, clock, clock_max;
148 int vid, vid_turbo, vid_min, vid_max, vid_range_2;
149 u32 control_status;
150 const struct pattrs *pattrs = pattrs_get();
151 msr_t msr;
152
153 /* Inputs from CPU attributes */
154 ratio_max = pattrs->iacore_ratios[IACORE_MAX];
155 ratio_min = pattrs->iacore_ratios[IACORE_LFM];
156 vid_max = pattrs->iacore_vids[IACORE_MAX];
157 vid_min = pattrs->iacore_vids[IACORE_LFM];
158
159 /* Set P-states coordination type based on MSR disable bit */
160 coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL;
161
162 /* Max Non-Turbo Frequency */
163 clock_max = (ratio_max * pattrs->bclk_khz) / 1000;
164
165 /* Calculate CPU TDP in mW */
166 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
167 power_unit = 1 << (msr.lo & 0xf);
168 msr = rdmsr(MSR_PKG_POWER_LIMIT);
169 power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
170
171 /* Write _PCT indicating use of FFixedHW */
172 acpigen_write_empty_PCT();
173
174 /* Write _PPC with NVS specified limit on supported P-state */
175 acpigen_write_PPC_NVS();
176
177 /* Write PSD indicating configured coordination type */
178 acpigen_write_PSD_package(core, 1, coord_type);
179
180 /* Add P-state entries in _PSS table */
181 acpigen_write_name("_PSS");
182
183 /* Determine ratio points */
184 ratio_step = 1;
185 num_entries = (ratio_max - ratio_min) / ratio_step;
186 while (num_entries > 15) { /* ACPI max is 15 ratios */
187 ratio_step <<= 1;
188 num_entries >>= 1;
189 }
190
191 /* P[T] is Turbo state if enabled */
192 if (get_turbo_state() == TURBO_ENABLED) {
193 /* _PSS package count including Turbo */
194 acpigen_write_package(num_entries + 2);
195
196 ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
197 vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
198 control_status = (ratio_turbo << 8) | vid_turbo;
199
200 /* Add entry for Turbo ratio */
201 acpigen_write_PSS_package(
202 clock_max + 1, /* MHz */
203 power_max, /* mW */
204 10, /* lat1 */
205 10, /* lat2 */
206 control_status, /* control */
207 control_status); /* status */
208 } else {
209 /* _PSS package count without Turbo */
210 acpigen_write_package(num_entries + 1);
211 ratio_turbo = ratio_max;
212 vid_turbo = vid_max;
213 }
214
215 /* First regular entry is max non-turbo ratio */
216 control_status = (ratio_max << 8) | vid_max;
217 acpigen_write_PSS_package(
218 clock_max, /* MHz */
219 power_max, /* mW */
220 10, /* lat1 */
221 10, /* lat2 */
222 control_status, /* control */
223 control_status); /* status */
224
225 /* Set up ratio and vid ranges for VID calculation */
226 ratio_range_2 = (ratio_turbo - ratio_min) * 2;
227 vid_range_2 = (vid_turbo - vid_min) * 2;
228
229 /* Generate the remaining entries */
230 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
231 ratio >= ratio_min; ratio -= ratio_step) {
232 /* Calculate VID for this ratio */
233 vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min;
234
235 /* Round up if remainder */
236 if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
237 vid++;
238
239 /* Calculate power at this ratio */
240 power = calculate_power(power_max, ratio_max, ratio);
241 clock = (ratio * pattrs->bclk_khz) / 1000;
242 control_status = (ratio << 8) | (vid & 0xff);
243
244 acpigen_write_PSS_package(
245 clock, /* MHz */
246 power, /* mW */
247 10, /* lat1 */
248 10, /* lat2 */
249 control_status, /* control */
250 control_status); /* status */
251 }
252
253 /* Fix package length */
254 acpigen_pop_len();
255 }
256
generate_cpu_entry(int core,int cores_per_package)257 static void generate_cpu_entry(int core, int cores_per_package)
258 {
259 /* Generate Scope(\_SB) { Device(CPUx */
260 acpigen_write_processor_device(core);
261
262 /* Generate P-state tables */
263 generate_p_state_entries(core);
264
265 /* Generate C-state tables */
266 acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map));
267
268 /* Generate T-state tables */
269 generate_t_state_entries(core, cores_per_package);
270
271 acpigen_write_processor_device_end();
272 }
273
generate_cpu_entries(const struct device * device)274 void generate_cpu_entries(const struct device *device)
275 {
276 int core;
277 const struct pattrs *pattrs = pattrs_get();
278
279 for (core = 0; core < pattrs->num_cpus; core++)
280 generate_cpu_entry(core, pattrs->num_cpus);
281
282 /* PPKG is usually used for thermal management
283 of the first and only package. */
284 acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus);
285
286 /* Add a method to notify processor nodes */
287 acpigen_write_processor_cnot(pattrs->num_cpus);
288 }
289