1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include <acpi/acpi_gnvs.h>
6 #include <console/console.h>
7 #include <device/device.h>
8 #include <device/pci.h>
9 #include <device/pci_ids.h>
10 #include <reg_script.h>
11
12 #include <soc/iomap.h>
13 #include <soc/iosf.h>
14 #include <soc/lpc.h>
15 #include <soc/device_nvs.h>
16 #include <soc/pattrs.h>
17 #include <soc/pci_devs.h>
18 #include <soc/pm.h>
19 #include <soc/ramstage.h>
20 #include "chip.h"
21
22 /*
23 * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
24 * address. Just take 1MiB @ 512MiB.
25 */
26 #define FIRMWARE_PHYS_BASE (512 << 20)
27 #define FIRMWARE_PHYS_LENGTH (1 << 20)
28 #define FIRMWARE_PCI_REG_BASE 0xa8
29 #define FIRMWARE_PCI_REG_LENGTH 0xac
30 #define FIRMWARE_REG_BASE_C0 0x144000
31 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
32
assign_device_nvs(struct device * dev,u32 * field,unsigned int index)33 static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index)
34 {
35 struct resource *res;
36
37 res = probe_resource(dev, index);
38 if (res)
39 *field = res->base;
40 }
41
lpe_enable_acpi_mode(struct device * dev)42 static void lpe_enable_acpi_mode(struct device *dev)
43 {
44 static const struct reg_script ops[] = {
45 /* Disable PCI interrupt, enable Memory and Bus Master */
46 REG_PCI_OR16(PCI_COMMAND,
47 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
48
49 /* Enable ACPI mode */
50 REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
51 LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN),
52
53 REG_SCRIPT_END
54 };
55 struct device_nvs *dev_nvs = acpi_get_device_nvs();
56
57 /* Save BAR0, BAR1, and firmware base to ACPI NVS */
58 assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0);
59 assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_1);
60 assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE);
61
62 /* Device is enabled in ACPI mode */
63 dev_nvs->lpe_en = 1;
64
65 /* Put device in ACPI mode */
66 reg_script_run_on_dev(dev, ops);
67 }
68
setup_codec_clock(struct device * dev)69 static void setup_codec_clock(struct device *dev)
70 {
71 uint32_t reg;
72 u32 *clk_reg;
73 struct soc_intel_baytrail_config *config;
74 const char *freq_str;
75
76 config = config_of(dev);
77 switch (config->lpe_codec_clk_freq) {
78 case 19:
79 freq_str = "19.2";
80 reg = CLK_FREQ_19P2MHZ;
81 break;
82
83 case 25:
84 freq_str = "25";
85 reg = CLK_FREQ_25MHZ;
86 break;
87
88 default:
89 printk(BIOS_DEBUG, "LPE codec clock not required.\n");
90 return;
91 }
92
93 /* Default to always running. */
94 reg |= CLK_CTL_ON;
95
96 if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
97 printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
98 return;
99 }
100
101 printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
102
103 clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
104 clk_reg += config->lpe_codec_clk_num;
105
106 write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
107 }
108
lpe_stash_firmware_info(struct device * dev)109 static void lpe_stash_firmware_info(struct device *dev)
110 {
111 struct resource *res;
112 struct resource *mmio;
113 const struct pattrs *pattrs = pattrs_get();
114
115 res = probe_resource(dev, FIRMWARE_PCI_REG_BASE);
116 if (res == NULL) {
117 printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
118 return;
119 }
120
121 /* Continue using old way of informing firmware address / size. */
122 pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
123 pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
124
125 /* C0 and later steppings use an offset in the MMIO space. */
126 if (pattrs->stepping >= STEP_C0) {
127 mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
128 write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
129 res->base);
130 write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
131 res->size);
132 }
133 }
134
lpe_init(struct device * dev)135 static void lpe_init(struct device *dev)
136 {
137 struct soc_intel_baytrail_config *config = config_of(dev);
138
139 lpe_stash_firmware_info(dev);
140 setup_codec_clock(dev);
141
142 if (config->lpe_acpi_mode)
143 lpe_enable_acpi_mode(dev);
144 }
145
lpe_read_resources(struct device * dev)146 static void lpe_read_resources(struct device *dev)
147 {
148 pci_dev_read_resources(dev);
149
150 reserved_ram_range(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE,
151 FIRMWARE_PHYS_LENGTH);
152 }
153
154 static const struct device_operations device_ops = {
155 .read_resources = lpe_read_resources,
156 .set_resources = pci_dev_set_resources,
157 .enable_resources = pci_dev_enable_resources,
158 .init = lpe_init,
159 .ops_pci = &soc_pci_ops,
160 };
161
162 static const struct pci_driver southcluster __pci_driver = {
163 .ops = &device_ops,
164 .vendor = PCI_VID_INTEL,
165 .device = LPE_DEVID,
166 };
167