1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <device/pci.h>
6 #include <delay.h>
7 #include <soc/pci_devs.h>
8 #include <soc/lpc.h>
9 #include <soc/iosf.h>
10 #include <soc/iomap.h>
11 #include <soc/ramstage.h>
12 #include <soc/modphy_table.h>
13
14 #define IOSF_READ(op_read, port) \
15 (IOSF_OPCODE(op_read) | IOSF_PORT(port))
16 #define IOSF_WRITE(op_write, port) \
17 (IOSF_OPCODE(op_write) | IOSF_PORT(port))
18
program_modphy_table(struct modphy_entry * table)19 static void program_modphy_table(struct modphy_entry *table)
20 {
21 u32 tmp;
22
23 for (; table->port; ++table) {
24 tmp = iosf_read_port(IOSF_READ(table->op_read, table->port), table->reg);
25 iosf_write_port(IOSF_WRITE(table->op_write, table->port), table->reg,
26 (tmp & table->mask) | table->value);
27 }
28 }
29
gpio_sc_sdcard_workaround(void)30 static void gpio_sc_sdcard_workaround(void)
31 {
32 setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0));
33 setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 2));
34 clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 1));
35 clrbits32((char *)IO_BASE_ADDRESS + 0x690, (1 << 3));
36 udelay(100);
37 clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0));
38 udelay(100);
39 write32((char *)IO_BASE_ADDRESS + 0x830, 0x78480);
40 udelay(40);
41 write32((char *)IO_BASE_ADDRESS + 0x830, 0x78080);
42 setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0));
43 udelay(100);
44 setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 1));
45 clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 2));
46 clrsetbits32((char *)IO_BASE_ADDRESS + 0x690, 7, (1 << 0));
47 }
48
49 #define BUNIT_BALIMIT0 0x0b
50 #define AUNIT_AVCCTL 0x21
51 #define AUNIT_ACFCACV 0x60
52 #define CUNIT_ACCESS_CTRL_VIOL 0x41
53 #define CUINT_SSA_REGIONAL_TRUNKGATE_CTL 0x43
54 #define TUNIT_CTL 0x03
55 #define TUNIT_MISC_CTL 0x04
56
ssa_safe_config(void)57 static void ssa_safe_config(void)
58 {
59 u32 tmp;
60
61 tmp = iosf_bunit_read(BUNIT_BALIMIT0);
62 iosf_bunit_write(BUNIT_BALIMIT0, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F);
63
64 tmp = iosf_aunit_read(AUNIT_AVCCTL);
65 iosf_aunit_write(AUNIT_AVCCTL, tmp | 0x80000100);
66
67 tmp = iosf_aunit_read(AUNIT_ACFCACV);
68 iosf_aunit_write(AUNIT_ACFCACV, tmp & 0x7FFFFFFF);
69
70 tmp = iosf_cunit_read(CUNIT_ACCESS_CTRL_VIOL);
71 iosf_cunit_write(CUNIT_ACCESS_CTRL_VIOL, tmp & 0x7FFFFFFF);
72
73 iosf_cunit_write(CUINT_SSA_REGIONAL_TRUNKGATE_CTL, 0x70008);
74
75 tmp = iosf_cpu_bus_read(TUNIT_CTL);
76 iosf_cpu_bus_write(TUNIT_CTL, tmp | 0x110430);
77
78 tmp = iosf_cpu_bus_read(TUNIT_MISC_CTL);
79 iosf_cpu_bus_write(TUNIT_MISC_CTL, tmp | 0x40010);
80 }
81
82 #define R_PCH_PMC_MTPMC1 0xb0
83
84 /*
85 * Replacement for refcode.elf
86 */
baytrail_run_reference_code(void)87 void baytrail_run_reference_code(void)
88 {
89 u32 tmp;
90 size_t pollcnt;
91
92 printk(BIOS_DEBUG, "ModPHY init entry\n");
93
94 if (pci_read_config8(pcidev_on_root(LPC_DEV, LPC_FUNC), REVID) < RID_B_STEPPING_START) {
95 printk(BIOS_DEBUG, "SOC A0/A1 ModPhy Table programming\n");
96 program_modphy_table(reva0_modphy_table);
97 } else {
98 printk(BIOS_DEBUG, "SOC B0 and later ModPhy Table programming\n");
99 program_modphy_table(revb0_modphy_table);
100 }
101
102 setbits32((char *)PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8);
103
104 for (pollcnt = 0; pollcnt < 10; ++pollcnt) {
105 tmp = read32((char *)PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1);
106 printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp);
107 if (!(tmp & 8))
108 break;
109 }
110
111 gpio_sc_sdcard_workaround();
112 ssa_safe_config();
113
114 printk(BIOS_DEBUG, "ModPHY init done\n");
115 }
116