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1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <arch/hpet.h>
4
5/* Intel LPC Bus Device  - 0:1f.0 */
6
7Device (LPCB)
8{
9	Name(_ADR, 0x001f0000)
10
11	#include "irqlinks.asl"
12
13	#include "acpi/ec.asl"
14
15	Device (DMAC)		/* DMA Controller */
16	{
17		Name(_HID, EISAID("PNP0200"))
18		Name(_CRS, ResourceTemplate()
19		{
20			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
21			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
22			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
23			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
24			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
25		})
26	}
27
28	Device (FWH)		/* Firmware Hub */
29	{
30		Name (_HID, EISAID("INT0800"))
31		Name (RBUF, ResourceTemplate()
32		{
33			Memory32Fixed(ReadOnly, 0, 0, FBAR)
34		})
35
36		Method (_CRS)
37		{
38			CreateDwordField (^RBUF, ^FBAR._BAS, FBAS)
39			CreateDwordField (^RBUF, ^FBAR._LEN, FLEN)
40			Local0 = CONFIG_COREBOOT_ROMSIZE_KB * 1024
41			FLEN = Local0
42			FBAS = 0xffffffff - Local0 + 1
43			Return (^RBUF)
44		}
45	}
46
47#if !CONFIG(DISABLE_HPET)
48	Device (HPET)
49	{
50		Name (_HID, EISAID("PNP0103"))
51		Name (_CID, 0x010CD041)
52
53		Method (_STA, 0)	/* Device Status */
54		{
55			Return (0xf)	/* Enable and show device */
56		}
57
58		Name(_CRS, ResourceTemplate()
59		{
60			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400)
61		})
62	}
63#endif
64
65	Device(PIC)	/* 8259 Interrupt Controller */
66	{
67		Name(_HID,EISAID("PNP0000"))
68		Name(_CRS, ResourceTemplate()
69		{
70			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
71			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
72			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
73			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
74			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
75			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
76			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
77			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
78			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
79			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
80			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
81			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
82			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
83			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
84			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
85			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
86			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
87			IRQNoFlags () { 2 }
88		})
89	}
90
91	Device(LDRC)	/* LPC device: Resource consumption */
92	{
93		Name (_HID, EISAID("PNP0C02"))
94		Name (_UID, 2)
95
96		Name (RBUF, ResourceTemplate()
97		{
98			IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
99			IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
100			IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
101			IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
102			IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
103			IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
104			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
105			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
106				0x1, ACPI_BASE_SIZE) /* ACPI Base */
107			IO (Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS,
108				0x1, 0xff) /* GPIO Base */
109		})
110
111		Method (_CRS, 0, NotSerialized)
112		{
113			Return (RBUF)
114		}
115	}
116
117	Device (RTC)	/* Real Time Clock */
118	{
119		Name (_HID, EISAID("PNP0B00"))
120		Name (_CRS, ResourceTemplate()
121		{
122			IO (Decode16, 0x70, 0x70, 1, 8)
123		})
124	}
125
126	Device (TIMR)	/* Intel 8254 timer */
127	{
128		Name(_HID, EISAID("PNP0100"))
129		Name(_CRS, ResourceTemplate()
130		{
131			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
132			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
133			IRQNoFlags() {0}
134		})
135	}
136
137	/* Include mainboard's superio.asl file. */
138	#include "acpi/superio.asl"
139}
140