1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/io.h>
4 #include <device/mmio.h>
5 #include <console/console.h>
6 #include <cpu/x86/smm.h>
7 #include <cpu/intel/smm_reloc.h>
8 #include <device/device.h>
9 #include <device/pci.h>
10 #include <soc/iomap.h>
11 #include <soc/pm.h>
12 #include <soc/smm.h>
13
14 /* Save settings which will be committed in SMI functions. */
15 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
16
smm_southcluster_save_param(int param,uint32_t data)17 void smm_southcluster_save_param(int param, uint32_t data)
18 {
19 smm_save_params[param] = data;
20 }
21
smm_southbridge_clear_state(void)22 void smm_southbridge_clear_state(void)
23 {
24 uint32_t smi_en;
25
26 /* Log events from chipset before clearing */
27 if (CONFIG(ELOG))
28 southcluster_log_state();
29
30 smi_en = inl(get_pmbase() + SMI_EN);
31 if (smi_en & APMC_EN) {
32 printk(BIOS_INFO, "SMI# handler already enabled?\n");
33 return;
34 }
35
36 /* Dump and clear status registers */
37 clear_smi_status();
38 clear_pm1_status();
39 clear_tco_status();
40 clear_gpe_status();
41 clear_alt_status();
42 clear_pmc_status();
43 }
44
smm_southcluster_route_gpios(void)45 static void smm_southcluster_route_gpios(void)
46 {
47 void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT);
48 const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
49 uint32_t alt_gpio_reg = 0;
50 uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];
51 int i;
52
53 printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg);
54
55 /* Start the routing for the specific gpios. */
56 write32(gpio_rout, route_reg);
57
58 /* Enable SMIs for the gpios that are set to trigger the SMI. */
59 for (i = 0; i < 16; i++) {
60 if ((route_reg & ROUTE_MASK) == ROUTE_SMI)
61 alt_gpio_reg |= (1 << i);
62
63 route_reg >>= 2;
64 }
65 printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg);
66
67 outl(alt_gpio_reg, alt_gpio_smi);
68 }
69
smm_southbridge_enable(uint16_t pm1_events)70 static void smm_southbridge_enable(uint16_t pm1_events)
71 {
72 printk(BIOS_DEBUG, "Enabling SMIs.\n");
73 if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
74 pm1_events |= PCIEXPWAK_DIS;
75
76 enable_pm1(pm1_events);
77 disable_gpe(PME_B0_EN);
78
79 /* Set up the GPIO route. */
80 smm_southcluster_route_gpios();
81
82 /*
83 * Enable SMI generation:
84 * - on APMC writes (io 0xb2)
85 * - on writes to SLP_EN (sleep states)
86 * - on writes to GBL_RLS (bios commands)
87 * No SMIs:
88 * - on TCO events
89 * - on microcontroller writes (io 0x62/0x66)
90 */
91 enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
92 }
93
global_smi_enable(void)94 void global_smi_enable(void)
95 {
96 smm_southbridge_enable(PWRBTN_EN | GBL_EN);
97 }
98