1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_BROADWELL 4 bool 5 select CACHE_MRC_SETTINGS 6 select CPU_INTEL_HASWELL 7 select INTEL_GMA_ACPI 8 select MRC_SETTINGS_PROTECT 9 select REG_SCRIPT 10 select TCO_SPACE_NOT_YET_SPLIT 11 select INTEL_LYNXPOINT_LP 12 help 13 Intel Broadwell and Haswell ULT support. 14 15if SOC_INTEL_BROADWELL 16 17config BROADWELL_LPDDR3 18 bool 19 help 20 Selected by mainboards using LPDDR3 DRAM to supply mainboard-specific 21 LPDDR3 DQ and DQS CPU-to-DRAM mapping info needed to perform raminit. 22 23config VBOOT 24 select VBOOT_MUST_REQUEST_DISPLAY 25 select VBOOT_STARTS_IN_BOOTBLOCK 26 27config ECAM_MMCONF_BASE_ADDRESS 28 default 0xf0000000 29 30config ECAM_MMCONF_BUS_NUMBER 31 default 64 32 33config VGA_BIOS_ID 34 string 35 default "8086,0406" 36 37config FIXED_MCHBAR_MMIO_BASE 38 default 0xfed10000 39 40config FIXED_DMIBAR_MMIO_BASE 41 default 0xfed18000 42 43config FIXED_EPBAR_MMIO_BASE 44 default 0xfed19000 45 46config DCACHE_RAM_BASE 47 hex 48 default 0xff7c0000 49 50config DCACHE_RAM_SIZE 51 hex 52 default 0x10000 53 help 54 The size of the cache-as-ram region required during bootblock 55 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE 56 must add up to a power of 2. 57 58config DCACHE_RAM_MRC_VAR_SIZE 59 hex 60 default 0x30000 61 help 62 The amount of cache-as-ram region required by the reference code. 63 64config DCACHE_BSP_STACK_SIZE 65 hex 66 default 0x2000 67 help 68 The amount of anticipated stack usage in CAR by bootblock and 69 other stages. 70 71config HAVE_MRC 72 bool "Add a Memory Reference Code binary" 73 help 74 Select this option to add a Memory Reference Code binary to 75 the resulting coreboot image. 76 77 Note: Without this binary coreboot will not work 78 79if HAVE_MRC 80 81config MRC_FILE 82 string "Intel Memory Reference Code path and filename" 83 depends on HAVE_MRC 84 default "mrc.bin" 85 help 86 The filename of the file to use as Memory Reference Code binary. 87 88config MRC_BIN_ADDRESS 89 hex 90 default 0xfffa0000 91 92# The UEFI System Agent binary needs to be at a fixed offset in the flash 93# and can therefore only reside in the COREBOOT fmap region 94config RO_REGION_ONLY 95 string 96 depends on VBOOT 97 default "mrc.bin" 98 99endif # HAVE_MRC 100 101config HAVE_REFCODE_BLOB 102 depends on ARCH_X86 103 bool "An external reference code blob should be put into cbfs." 104 default n 105 help 106 The reference code blob will be placed into cbfs. 107 108if HAVE_REFCODE_BLOB 109 110config REFCODE_BLOB_FILE 111 string "Path and filename to reference code blob." 112 default "refcode.elf" 113 help 114 The path and filename to the file to be added to cbfs. 115 116endif # HAVE_REFCODE_BLOB 117 118source "src/soc/intel/broadwell/pch/Kconfig" 119 120endif 121