1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <arch/bootblock.h> 4 #include <assert.h> 5 #include <device/pci_ops.h> 6 #include <soc/pci_devs.h> 7 #include <soc/systemagent.h> 8 encode_pciexbar_length(void)9static uint32_t encode_pciexbar_length(void) 10 { 11 switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { 12 case 256: return 0 << 1; 13 case 128: return 1 << 1; 14 case 64: return 2 << 1; 15 default: return dead_code_t(uint32_t); 16 } 17 } 18 bootblock_early_northbridge_init(void)19void bootblock_early_northbridge_init(void) 20 { 21 /* 22 * The "io" variant of the config access is explicitly used to setup the 23 * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all 24 * subsequent non-explicit config accesses use MCFG. This code also assumes 25 * that bootblock_northbridge_init() is the first thing called in the non-asm 26 * boot block code. The final assumption is that no assembly code is using the 27 * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. 28 * 29 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. 30 */ 31 const uint32_t reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; 32 pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); 33 pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); 34 } 35