1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /* Use simple device model for this file even in ramstage */
4 #define __SIMPLE_DEVICE__
5
6 #include <arch/romstage.h>
7 #include <cbmem.h>
8 #include <cpu/x86/smm.h>
9 #include <device/pci.h>
10 #include <device/pci_ops.h>
11 #include <soc/pci_devs.h>
12 #include <soc/systemagent.h>
13 #include <stdint.h>
14
dpr_region_start(void)15 static uintptr_t dpr_region_start(void)
16 {
17 /*
18 * Base of DPR is top of usable DRAM below 4GiB. The register has
19 * 1 MiB alignment and reports the TOP of the range, the base
20 * must be calculated from the size in MiB in bits 11:4.
21 */
22 uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR);
23 uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB);
24
25 /* Subtract DMA Protected Range size if enabled */
26 if (dpr & DPR_EPM)
27 tom -= (dpr & DPR_SIZE_MASK) << 16;
28
29 return tom;
30 }
31
cbmem_top_chipset(void)32 uintptr_t cbmem_top_chipset(void)
33 {
34 return dpr_region_start();
35 }
36
smm_region(uintptr_t * start,size_t * size)37 void smm_region(uintptr_t *start, size_t *size)
38 {
39 uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG);
40 uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM);
41
42 tseg = ALIGN_DOWN(tseg, 1 * MiB);
43 bgsm = ALIGN_DOWN(bgsm, 1 * MiB);
44 *start = tseg;
45 *size = bgsm - tseg;
46 }
47
fill_postcar_frame(struct postcar_frame * pcf)48 void fill_postcar_frame(struct postcar_frame *pcf)
49 {
50 /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
51 * above top of the ram. This satisfies MTRR alignment requirement
52 * with different TSEG size configurations.
53 */
54 const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
55 postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
56 MTRR_TYPE_WRBACK);
57 }
58