1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <cbfs.h>
5 #include <cbmem.h>
6 #include <cf9_reset.h>
7 #include <console/console.h>
8 #include <device/pci_def.h>
9 #include <memory_info.h>
10 #include <mrc_cache.h>
11 #include <string.h>
12 #include <soc/iomap.h>
13 #include <soc/pei_data.h>
14 #include <soc/pei_wrapper.h>
15 #include <soc/pm.h>
16 #include <soc/romstage.h>
17 #include <soc/systemagent.h>
18 #include <timestamp.h>
19 #include <types.h>
20
save_mrc_data(struct pei_data * pei_data)21 static void save_mrc_data(struct pei_data *pei_data)
22 {
23 printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
24 pei_data->data_to_save_size);
25
26 if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0)
27 mrc_cache_stash_data(MRC_TRAINING_DATA, 0,
28 pei_data->data_to_save,
29 pei_data->data_to_save_size);
30 }
31
32 static const char *const ecc_decoder[] = {
33 "inactive",
34 "active on IO",
35 "disabled on IO",
36 "active",
37 };
38
39 /*
40 * Dump in the log memory controller configuration as read from the memory
41 * controller registers.
42 */
report_memory_config(void)43 static void report_memory_config(void)
44 {
45 int i;
46
47 const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
48
49 printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
50 DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100));
51
52 printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
53 (addr_decoder_common >> 0) & 3,
54 (addr_decoder_common >> 2) & 3,
55 (addr_decoder_common >> 4) & 3);
56
57 for (i = 0; i < NUM_CHANNELS; i++) {
58 const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
59
60 printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
61 printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
62 printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
63 ((ch_conf >> 22) & 1) ? "on" : "off");
64
65 printk(BIOS_DEBUG, " rank interleave %s\n",
66 ((ch_conf >> 21) & 1) ? "on" : "off");
67
68 printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
69 ((ch_conf >> 0) & 0xff) * 256,
70 ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
71 ((ch_conf >> 17) & 1) ? "dual" : "single",
72 ((ch_conf >> 16) & 1) ? "" : ", selected");
73
74 printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
75 ((ch_conf >> 8) & 0xff) * 256,
76 ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
77 ((ch_conf >> 18) & 1) ? "dual" : "single",
78 ((ch_conf >> 16) & 1) ? ", selected" : "");
79 }
80 }
81
82 /*
83 * Find PEI executable in coreboot filesystem and execute it.
84 */
sdram_initialize(struct pei_data * pei_data)85 static void sdram_initialize(struct pei_data *pei_data)
86 {
87 size_t mrc_size;
88 pei_wrapper_entry_t entry;
89 int ret;
90
91 broadwell_fill_pei_data(pei_data);
92
93 /* Assume boot device is memory mapped. */
94 assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
95
96 pei_data->saved_data =
97 mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
98 &mrc_size);
99 if (pei_data->saved_data) {
100 /* MRC cache found */
101 pei_data->saved_data_size = mrc_size;
102 } else if (pei_data->boot_mode == ACPI_S3) {
103 /* Waking from S3 and no cache. */
104 printk(BIOS_DEBUG,
105 "No MRC cache found in S3 resume path.\n");
106 post_code(POSTCODE_RESUME_FAILURE);
107 system_reset();
108 } else {
109 printk(BIOS_DEBUG, "No MRC cache found.\n");
110 }
111
112 /*
113 * Do not use saved pei data. Can be set by mainboard romstage
114 * to force a full train of memory on every boot.
115 */
116 if (pei_data->disable_saved_data) {
117 printk(BIOS_DEBUG, "Disabling PEI saved data by request\n");
118 pei_data->saved_data = NULL;
119 pei_data->saved_data_size = 0;
120 }
121
122 /* We don't care about leaking the mapping */
123 entry = cbfs_ro_map("mrc.bin", NULL);
124 if (entry == NULL)
125 die("mrc.bin not found!");
126
127 printk(BIOS_DEBUG, "Starting Memory Reference Code\n");
128
129 ret = entry(pei_data);
130 if (ret < 0)
131 die("pei_data version mismatch\n");
132
133 /* Print the MRC version after executing the UEFI PEI stage. */
134 u32 version = mchbar_read32(MRC_REVISION);
135 printk(BIOS_DEBUG, "MRC Version %u.%u.%u Build %u\n",
136 (version >> 24) & 0xff, (version >> 16) & 0xff,
137 (version >> 8) & 0xff, (version >> 0) & 0xff);
138
139 report_memory_config();
140 }
141
setup_sdram_meminfo(struct pei_data * pei_data)142 static void setup_sdram_meminfo(struct pei_data *pei_data)
143 {
144 struct memory_info *mem_info;
145
146 printk(BIOS_DEBUG, "create cbmem for dimm information\n");
147 mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
148
149 if (!mem_info) {
150 printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n");
151 return;
152 }
153
154 memset(mem_info, 0, sizeof(*mem_info));
155 /* Translate pei_memory_info struct data into memory_info struct */
156 mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt;
157 for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) {
158 struct dimm_info *dimm = &mem_info->dimm[i];
159 const struct pei_dimm_info *pei_dimm =
160 &pei_data->meminfo.dimm[i];
161 dimm->dimm_size = pei_dimm->dimm_size;
162 dimm->ddr_type = pei_dimm->ddr_type;
163 dimm->ddr_frequency = pei_dimm->ddr_frequency;
164 dimm->rank_per_dimm = pei_dimm->rank_per_dimm;
165 dimm->channel_num = pei_dimm->channel_num;
166 dimm->dimm_num = pei_dimm->dimm_num;
167 dimm->bank_locator = pei_dimm->bank_locator;
168 memcpy(&dimm->serial, &pei_dimm->serial,
169 MIN(sizeof(dimm->serial), sizeof(pei_dimm->serial)));
170 memcpy(&dimm->module_part_number,
171 &pei_dimm->module_part_number,
172 MIN(sizeof(dimm->module_part_number),
173 sizeof(pei_dimm->module_part_number)));
174 dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0';
175 dimm->mod_id = pei_dimm->mod_id;
176 dimm->mod_type = pei_dimm->mod_type;
177 dimm->bus_width = pei_dimm->bus_width;
178 }
179 }
180
181 /*
182 * 0 = leave channel enabled
183 * 1 = disable dimm 0 on channel
184 * 2 = disable dimm 1 on channel
185 * 3 = disable dimm 0+1 on channel
186 */
make_channel_disabled_mask(const struct spd_info * spdi,int ch)187 static int make_channel_disabled_mask(const struct spd_info *spdi, int ch)
188 {
189 return (!spdi->addresses[ch + ch] << 0) | (!spdi->addresses[ch + ch + 1] << 1);
190 }
191
perform_raminit(const struct chipset_power_state * const power_state)192 void perform_raminit(const struct chipset_power_state *const power_state)
193 {
194 const int s3resume = power_state->prev_sleep_state == ACPI_S3;
195
196 struct pei_data pei_data = { 0 };
197
198 mainboard_fill_pei_data(&pei_data);
199
200 if (CONFIG(BROADWELL_LPDDR3)) {
201 const struct lpddr3_dq_dqs_map *lpddr3_map = mb_get_lpddr3_dq_dqs_map();
202 assert(lpddr3_map);
203 memcpy(pei_data.dq_map, lpddr3_map->dq, sizeof(pei_data.dq_map));
204 memcpy(pei_data.dqs_map, lpddr3_map->dqs, sizeof(pei_data.dqs_map));
205 }
206
207 /* Obtain the SPD addresses from mainboard code */
208 struct spd_info spdi = { 0 };
209 mb_get_spd_map(&spdi);
210
211 if (CONFIG(HAVE_SPD_IN_CBFS))
212 copy_spd(&pei_data, &spdi);
213
214 /* Calculate unimplemented DIMM slots for each channel */
215 pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&spdi, 0);
216 pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&spdi, 1);
217
218 /* MRC expects left-aligned SMBus addresses, and 0 for memory-down */
219 for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) {
220 const uint8_t addr = spdi.addresses[i];
221 pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0 : addr << 1;
222 }
223
224 post_code(0x32);
225
226 timestamp_add_now(TS_INITRAM_START);
227
228 pei_data.boot_mode = power_state->prev_sleep_state;
229
230 /* Initialize RAM */
231 sdram_initialize(&pei_data);
232
233 timestamp_add_now(TS_INITRAM_END);
234
235 int cbmem_was_initted = !cbmem_recovery(s3resume);
236 if (s3resume && !cbmem_was_initted) {
237 /* Failed S3 resume, reset to come up cleanly */
238 printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
239 system_reset();
240 }
241
242 save_mrc_data(&pei_data);
243
244 setup_sdram_meminfo(&pei_data);
245 }
246