1## SPDX-License-Identifier: GPL-2.0-only 2ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_BASE),y) 3 4subdirs-y += romstage 5subdirs-y += ../../../cpu/intel/microcode 6subdirs-y += ../../../cpu/intel/turbo 7subdirs-y += ../../../cpu/intel/common 8 9bootblock-y += bootblock/bootblock.c 10bootblock-y += bootblock/pch.c 11bootblock-y += pmutil.c 12bootblock-y += bootblock/report_platform.c 13bootblock-y += gspi.c 14bootblock-y += i2c.c 15bootblock-y += spi.c 16bootblock-y += lpc.c 17bootblock-y += p2sb.c 18bootblock-y += uart.c 19 20romstage-y += cnl_memcfg_init.c 21romstage-y += gspi.c 22romstage-y += i2c.c 23romstage-y += lpc.c 24romstage-y += pmutil.c 25romstage-y += reset.c 26romstage-y += spi.c 27romstage-y += uart.c 28 29ramstage-y += acpi.c 30ramstage-y += chip.c 31ramstage-y += cpu.c 32ramstage-y += elog.c 33ramstage-y += finalize.c 34ramstage-y += fsp_params.c 35ramstage-y += graphics.c 36ramstage-y += gspi.c 37ramstage-y += i2c.c 38ramstage-y += lockdown.c 39ramstage-y += lpc.c 40ramstage-y += nhlt.c 41ramstage-y += p2sb.c 42ramstage-y += pmc.c 43ramstage-y += pmutil.c 44ramstage-y += reset.c 45ramstage-y += spi.c 46ramstage-y += systemagent.c 47ramstage-y += uart.c 48ramstage-y += vr_config.c 49ramstage-y += sd.c 50ramstage-y += xhci.c 51 52smm-y += elog.c 53smm-y += p2sb.c 54smm-y += pmutil.c 55smm-y += smihandler.c 56smm-y += uart.c 57smm-y += xhci.c 58 59postcar-y += pmutil.c 60postcar-y += i2c.c 61postcar-y += gspi.c 62postcar-y += spi.c 63postcar-y += uart.c 64 65verstage-y += gspi.c 66verstage-y += i2c.c 67verstage-y += pmutil.c 68verstage-y += spi.c 69verstage-y += uart.c 70 71ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) 72bootblock-y += gpio_cnp_h.c 73romstage-y += gpio_cnp_h.c 74ramstage-y += gpio_cnp_h.c 75smm-y += gpio_cnp_h.c 76verstage-y += gpio_cnp_h.c 77else 78bootblock-y += gpio.c 79romstage-y += gpio.c 80ramstage-y += gpio.c 81smm-y += gpio.c 82verstage-y += gpio.c 83endif 84 85bootblock-y += gpio_common.c 86ramstage-y += gpio_common.c 87 88romstage-$(CONFIG_SOC_INTEL_COMETLAKE_1_2) += cometlake_1_2.c 89ramstage-$(CONFIG_SOC_INTEL_COMETLAKE_1_2) += cometlake_1_2.c 90 91ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y) 92ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) 93cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0a 94cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0b 95cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0c 96cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0d 97else 98cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a 99endif 100else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y) 101cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b 102cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c 103else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y) 104ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) 105cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-02 106cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-03 107cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-05 108else 109cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c 110cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a6-00 111cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a6-01 112endif 113endif 114 115CPPFLAGS_common += -I$(src)/soc/intel/cannonlake 116CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include 117 118# DSP firmware settings files. 119NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs 120DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin 121DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin 122DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin 123MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin 124DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin 125MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin 126MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin 127 128cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B) 129$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B) 130$(DMIC_1CH_48KHZ_16B)-type := raw 131 132cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) 133$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) 134$(DMIC_2CH_48KHZ_16B)-type := raw 135 136cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) 137$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) 138$(DMIC_4CH_48KHZ_16B)-type := raw 139 140cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) 141$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) 142$(MAX98357_RENDER)-type := raw 143 144cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_16B) 145$(MAX98373_RENDER_16B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_16B) 146$(MAX98373_RENDER_16B)-type := raw 147 148cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_24B) 149$(MAX98373_RENDER_24B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_24B) 150$(MAX98373_RENDER_24B)-type := raw 151 152cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) 153$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) 154$(DA7219_RENDER_CAPTURE)-type := raw 155 156endif 157