1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_CHIP_H_ 4 #define _SOC_CHIP_H_ 5 6 #include <drivers/i2c/designware/dw_i2c.h> 7 #include <drivers/intel/gma/gma.h> 8 #include <gpio.h> 9 #include <intelblocks/cfg.h> 10 #include <intelblocks/gspi.h> 11 #include <intelblocks/lpc_lib.h> 12 #include <intelblocks/power_limit.h> 13 #include <intelblocks/xhci.h> 14 #include <stdbool.h> 15 #include <stdint.h> 16 #include <soc/pch.h> 17 #include <soc/pci_devs.h> 18 #include <soc/pm.h> 19 #include <soc/pmc.h> 20 #include <soc/sata.h> 21 #include <soc/serialio.h> 22 #include <soc/usb.h> 23 #include <soc/vr_config.h> 24 #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) 25 #include <soc/gpio_defs_cnp_h.h> 26 #else 27 #include <soc/gpio_defs.h> 28 #endif 29 30 #define SOC_INTEL_CML_UART_DEV_MAX 3 31 #define SOC_INTEL_CML_SATA_DEV_MAX 8 32 33 enum chip_pl2_4_cfg { 34 baseline, 35 performance, 36 value_not_set /* vr_config internal use only */ 37 }; 38 39 struct soc_intel_cannonlake_config { 40 /* Common struct containing soc config data required by common code */ 41 struct soc_intel_common_config common_soc_config; 42 43 /* Common struct containing power limits configuration information */ 44 struct soc_power_limits_config power_limits_config; 45 46 /* Gpio group routed to each dword of the GPE0 block. Values are 47 * of the form GPP_[A:G] or GPD. */ 48 uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ 49 uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ 50 uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ 51 52 /* Generic IO decode ranges */ 53 uint32_t gen1_dec; 54 uint32_t gen2_dec; 55 uint32_t gen3_dec; 56 uint32_t gen4_dec; 57 58 /* S0ix configuration */ 59 60 /* Enable S0iX support */ 61 bool s0ix_enable; 62 /* Enable Audio DSP oscillator qualification for S0ix */ 63 bool cppmvric2_adsposcdis; 64 65 /* Enable DPTF support */ 66 bool dptf_enable; 67 68 enum { 69 MAX_PC_DEFAULT = 0, 70 MAX_PC0_1 = 1, 71 MAX_PC2 = 2, 72 MAX_PC3 = 3, 73 MAX_PC6 = 4, 74 MAX_PC7 = 5, 75 MAX_PC7S = 6, 76 MAX_PC8 = 7, 77 MAX_PC9 = 8, 78 MAX_PC10 = 9, 79 } max_package_c_state; 80 81 /* Deep SX enable for both AC and DC */ 82 bool deep_s3_enable_ac; 83 bool deep_s3_enable_dc; 84 bool deep_s5_enable_ac; 85 bool deep_s5_enable_dc; 86 87 /* Deep Sx Configuration 88 * DSX_EN_WAKE_PIN - Enable WAKE# pin 89 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin 90 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ 91 uint32_t deep_sx_config; 92 93 /* TCC activation offset */ 94 uint32_t tcc_offset; 95 96 /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. 97 * For CNL, options are as following 98 * When enabled, memory will be training at three different frequencies. 99 * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled 100 * For WHL/CFL/CML options are as following 101 * When enabled, memory will be training at two different frequencies. 102 * 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/ 103 enum { 104 SaGv_Disabled, 105 SaGv_FixedLow, 106 SaGv_FixedHigh, 107 SaGv_Enabled, 108 } SaGv; 109 110 /* Rank Margin Tool. 1:Enable, 0:Disable */ 111 bool RMT; 112 113 /* USB related */ 114 struct usb2_port_config usb2_ports[16]; 115 struct usb3_port_config usb3_ports[10]; 116 /* Wake Enable Bitmap for USB2 ports */ 117 uint16_t usb2_wake_enable_bitmap; 118 /* Wake Enable Bitmap for USB3 ports */ 119 uint16_t usb3_wake_enable_bitmap; 120 /* USB2 PHY power gating */ 121 bool PchUsb2PhySusPgDisable; 122 123 /* SATA related */ 124 enum { 125 SATA_AHCI, 126 SATA_RAID, 127 } SataMode; 128 129 /* SATA devslp pad reset configuration */ 130 enum { 131 SataDevSlpResumeReset = 1, 132 SataDevSlpHostDeepReset = 3, 133 SataDevSlpPlatformReset = 5, 134 SataDevSlpDswReset = 7 135 } SataDevSlpRstConfig; 136 137 bool SataSalpSupport; 138 bool SataPortsEnable[8]; 139 bool SataPortsDevSlp[8]; 140 uint8_t SataPortsDevSlpResetConfig[8]; 141 bool SataPortsHotPlug[8]; 142 143 /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ 144 bool SlpS0WithGbeSupport; 145 /* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */ 146 bool PchPmSlpS0VmRuntimeControl; 147 /* SLP_S0 Voltage Margining 0.70V Policy. 0: disable, 1: enable */ 148 bool PchPmSlpS0Vm070VSupport; 149 /* SLP_S0 Voltage Margining 0.75V Policy. 0: disable, 1: enable */ 150 bool PchPmSlpS0Vm075VSupport; 151 152 /* Audio related */ 153 bool PchHdaDspEnable; 154 155 /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ 156 bool PchHdaAudioLinkHda; 157 bool PchHdaIDispCodecDisconnect; 158 bool PchHdaAudioLinkDmic0; 159 bool PchHdaAudioLinkDmic1; 160 bool PchHdaAudioLinkSsp0; 161 bool PchHdaAudioLinkSsp1; 162 bool PchHdaAudioLinkSsp2; 163 bool PchHdaAudioLinkSndw1; 164 bool PchHdaAudioLinkSndw2; 165 bool PchHdaAudioLinkSndw3; 166 bool PchHdaAudioLinkSndw4; 167 168 /* PCIe Root Ports */ 169 bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; 170 /* PCIe output clocks type to PCIe devices. 171 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, 172 * 0xFF: not used */ 173 uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; 174 /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to 175 * clksrc. */ 176 uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; 177 /* PCIe LTR(Latency Tolerance Reporting) mechanism */ 178 bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; 179 /* Implemented as slot or built-in? */ 180 bool PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; 181 /* Enable/Disable HotPlug support for Root Port */ 182 bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; 183 184 /* 185 * Enable/Disable AER (Advanced Error Reporting) for Root Port 186 * 0: Disable AER 187 * 1: Enable AER 188 */ 189 bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; 190 191 /* PCIE RP ASPM, ASPM support for the root port */ 192 enum { 193 AspmDefault, 194 AspmDisabled, 195 AspmL0s, 196 AspmL1, 197 AspmL0sL1, 198 AspmAutoConfig, 199 } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; 200 201 /* PCIE RP Max Payload, Max Payload Size supported */ 202 enum { 203 RpMaxPayload_128, 204 RpMaxPayload_256, 205 } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; 206 207 /* eMMC and SD */ 208 bool ScsEmmcHs400Enabled; 209 /* Need to update DLL setting to get Emmc running at HS400 speed */ 210 bool EmmcHs400DllNeed; 211 /* 0-39: number of active delay for RX strobe, unit is 125 psec */ 212 uint8_t EmmcHs400RxStrobeDll1; 213 /* 0-78: number of active delay for TX data, unit is 125 psec */ 214 uint8_t EmmcHs400TxDataDll; 215 /* Enable/disable SD card write protect pin configuration on CML */ 216 bool ScsSdCardWpPinEnabled; 217 218 /* Heci related */ 219 bool DisableHeciRetry; 220 221 /* Gfx related */ 222 bool SkipExtGfxScan; 223 224 bool Device4Enable; 225 226 /* CPU PL2/4 Config 227 * Performance: Maximum PLs for maximum performance. 228 * Baseline: Baseline PLs for balanced performance at lower power. 229 */ 230 enum chip_pl2_4_cfg cpu_pl2_4_cfg; 231 232 /* VrConfig Settings for 5 domains 233 * 0 = System Agent, 1 = IA Core, 2 = Ring, 234 * 3 = GT unsliced, 4 = GT sliced */ 235 struct vr_config domain_vr_config[NUM_VR_DOMAINS]; 236 237 /* Enables support for Teton Glacier hybrid storage device */ 238 bool TetonGlacierMode; 239 240 /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ 241 bool eist_enable; 242 243 /* Enable C6 DRAM */ 244 bool enable_c6dram; 245 246 /* 247 * SLP_S3 Minimum Assertion Width Policy 248 * 1 = 60us 249 * 2 = 1ms (default) 250 * 3 = 50ms 251 * 4 = 2s 252 */ 253 uint8_t PchPmSlpS3MinAssert; 254 255 /* 256 * SLP_S4 Minimum Assertion Width Policy 257 * 1 = 1s 258 * 2 = 2s 259 * 3 = 3s 260 * 4 = 4s (default) 261 */ 262 uint8_t PchPmSlpS4MinAssert; 263 264 /* 265 * SLP_SUS Minimum Assertion Width Policy 266 * 1 = 0ms 267 * 2 = 500ms 268 * 3 = 1s (default) 269 * 4 = 4s 270 */ 271 uint8_t PchPmSlpSusMinAssert; 272 273 /* 274 * SLP_A Minimum Assertion Width Policy 275 * 1 = 0ms 276 * 2 = 4s 277 * 3 = 98ms (default) 278 * 4 = 2s 279 */ 280 uint8_t PchPmSlpAMinAssert; 281 282 /* 283 * PCH PM Reset Power Cycle Duration 284 * 0 = 4s 285 * 1 = 1s 286 * 2 = 2s 287 * 3 = 3s 288 * 4 = 4s (default) 289 * 290 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the 291 * stretch duration programmed in the following registers - 292 * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) 293 * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) 294 * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) 295 * - PM_CFG.SLP_LAN_MIN_ASST_WDTH 296 */ 297 uint8_t PchPmPwrCycDur; 298 299 /* 300 * SerialIO device mode selection: 301 * 302 * Device index: 303 * PchSerialIoIndexI2C0 304 * PchSerialIoIndexI2C1 305 * PchSerialIoIndexI2C2 306 * PchSerialIoIndexI2C3 307 * PchSerialIoIndexI2C4 308 * PchSerialIoIndexI2C5 309 * PchSerialIoIndexSPI0 310 * PchSerialIoIndexSPI1 311 * PchSerialIoIndexSPI2 312 * PchSerialIoIndexUART0 313 * PchSerialIoIndexUART1 314 * PchSerialIoIndexUART2 315 * 316 * Mode select: 317 * For Cannonlake PCH following values are supported: 318 * PchSerialIoNotInitialized 319 * PchSerialIoDisabled 320 * PchSerialIoPci 321 * PchSerialIoAcpi 322 * PchSerialIoHidden 323 * PchSerialIoMax 324 * 325 * For Cometlake following values are supported: 326 * PchSerialIoNotInitialized 327 * PchSerialIoDisabled, 328 * PchSerialIoPci, 329 * PchSerialIoHidden, 330 * PchSerialIoLegacyUart, 331 * PchSerialIoSkipInit, 332 * PchSerialIoMax 333 * 334 * NOTE: 335 * PchSerialIoNotInitialized is not an option provided by FSP, this 336 * option is default selected in case devicetree doesn't fill this param 337 * In case PchSerialIoNotInitialized is selected or an invalid value is 338 * provided from devicetree, coreboot will configure device into PCI 339 * mode by default. 340 * 341 */ 342 uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; 343 344 enum serirq_mode serirq_mode; 345 346 /* GPIO SD card detect pin */ 347 unsigned int sdcard_cd_gpio; 348 349 /* Enable Pch iSCLK */ 350 bool pch_isclk; 351 352 /* 353 * Acoustic Noise Mitigation 354 * 0b - Disable 355 * 1b - Enable noise mitigation 356 */ 357 bool AcousticNoiseMitigation; 358 359 /* 360 * Disable Fast Package C-state ramping 361 * Need to set AcousticNoiseMitigation = '1' first 362 * 0b - Enabled 363 * 1b - Disabled 364 */ 365 bool FastPkgCRampDisableIa; 366 bool FastPkgCRampDisableGt; 367 bool FastPkgCRampDisableSa; 368 bool FastPkgCRampDisableFivr; 369 370 /* 371 * Adjust the VR slew rates 372 * Need to set AcousticNoiseMitigation = '1' first 373 * 000b - Fast/2 374 * 001b - Fast/4 375 * 010b - Fast/8 376 * 011b - Fast/16 377 */ 378 uint8_t SlowSlewRateForIa; 379 uint8_t SlowSlewRateForGt; 380 uint8_t SlowSlewRateForSa; 381 uint8_t SlowSlewRateForFivr; 382 383 /* SATA Power Optimizer */ 384 bool satapwroptimize; 385 386 /* SATA Gen3 Strength */ 387 struct sata_port_config sata_port[SOC_INTEL_CML_SATA_DEV_MAX]; 388 389 /* Enable or disable eDP device */ 390 bool DdiPortEdp; 391 392 /* Enable or disable HPD of DDI port B/C/D/F */ 393 bool DdiPortBHpd; 394 bool DdiPortCHpd; 395 bool DdiPortDHpd; 396 bool DdiPortFHpd; 397 398 /* Enable or disable DDC of DDI port B/C/D/F */ 399 bool DdiPortBDdc; 400 bool DdiPortCDdc; 401 bool DdiPortDDdc; 402 bool DdiPortFDdc; 403 404 /* Unlock all GPIO Pads */ 405 bool PchUnlockGpioPads; 406 407 /* Enable GBE wakeup */ 408 bool LanWakeFromDeepSx; 409 bool WolEnableOverride; 410 411 #if !CONFIG(SOC_INTEL_COMETLAKE) 412 uint32_t VrPowerDeliveryDesign; 413 #endif 414 415 /* 416 * Override GPIO PM configuration: 417 * 0: Use FSP default GPIO PM program, 418 * 1: coreboot to override GPIO PM program 419 */ 420 bool gpio_override_pm; 421 /* 422 * GPIO PM configuration: 0 to disable, 1 to enable power gating 423 * Bit 6-7: Reserved 424 * Bit 5: MISCCFG_GPSIDEDPCGEN 425 * Bit 4: MISCCFG_GPRCOMPCDLCGEN 426 * Bit 3: MISCCFG_GPRTCDLCGEN 427 * Bit 2: MISCCFG_GSXLCGEN 428 * Bit 1: MISCCFG_GPDPCGEN 429 * Bit 0: MISCCFG_GPDLCGEN 430 */ 431 uint8_t gpio_pm[TOTAL_GPIO_COMM]; 432 433 /* 434 * Override CPU flex ratio value: 435 * CPU ratio value controls the maximum processor non-turbo ratio. 436 * Valid Range 0 to 63. 437 * 438 * In general descriptor provides option to set default cpu flex ratio. 439 * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. 440 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. 441 * 442 * Only override CPU flex ratio if don't want to boot with non-turbo max. 443 */ 444 uint8_t cpu_ratio_override; 445 446 struct i915_gpu_panel_config panel_cfg; 447 448 struct i915_gpu_controller_info gfx; 449 450 /* Disable CPU Turbo in IA32_MISC_ENABLE */ 451 bool cpu_turbo_disable; 452 453 bool disable_vmx; 454 }; 455 456 typedef struct soc_intel_cannonlake_config config_t; 457 458 #endif 459